L-Tile and H-Tile Avalon® Memory-mapped+ Intel® FPGA IP for PCI Express* User Guide

ID 683527
Date 3/05/2024
Public
Document Table of Contents

3.2.3.3. Interrupts

The Intel L-/H-Tile Avalon-MM+ for PCI Express IP does not use the interrupt-related signals described in the next section. However, the user application logic can use them to generate or respond to interrupts.