L-Tile and H-Tile Avalon® Memory-mapped+ Intel® FPGA IP for PCI Express* User Guide
ID
683527
Date
9/13/2024
Public
1. Introduction
2. Quick Start Guide
3. Block and Interface Descriptions
4. Parameters
5. Designing with the IP Core
6. Registers
7. Design Example and Testbench
8. Document Revision History for Intel® L- and H-tile Avalon® Memory-mapped+ IP for PCI Express* User Guide
A. Avalon-MM IP Variants Comparison
B. Root Port BFM
C. BFM Procedures and Functions
D. Troubleshooting and Observing the Link Status
E. Root Port Enumeration
2.1. Design Components
2.2. Directory Structure
2.3. Generating the Design Example
2.4. Simulating the Design Example
2.5. Compiling the Design Example and Programming the Device
2.6. Installing the Linux Kernel Driver
2.7. Running the Design Example Application
2.8. Ensuring the Design Example Meets Timing Requirements
6.1.1. Register Access Definitions
6.1.2. PCI Configuration Header Registers
6.1.3. PCI Express Capability Structures
6.1.4. Intel Defined VSEC Capability Header
6.1.5. Uncorrectable Internal Error Status Register
6.1.6. Uncorrectable Internal Error Mask Register
6.1.7. Correctable Internal Error Status Register
6.1.8. Correctable Internal Error Mask Register
C.1. ebfm_barwr Procedure
C.2. ebfm_barwr_imm Procedure
C.3. ebfm_barrd_wait Procedure
C.4. ebfm_barrd_nowt Procedure
C.5. ebfm_cfgwr_imm_wait Procedure
C.6. ebfm_cfgwr_imm_nowt Procedure
C.7. ebfm_cfgrd_wait Procedure
C.8. ebfm_cfgrd_nowt Procedure
C.9. BFM Configuration Procedures
C.10. BFM Shared Memory Access Procedures
C.11. BFM Log and Message Procedures
C.12. Verilog HDL Formatting Functions
7.1.1.1. DMA Controller (DMA Example Design Only)
The DMA Controller in this example design consists of six addressable queues: two write-only queues and one read-only queue each for the Read Data Mover and the Write Data Mover. In addition, the DMA Controller has two MSI control registers for each Data Mover module.
The write-only queues directly feed into the Data Movers’ normal and priority descriptor queues. The read-only queues read directly from the Data Movers’ status queues.
The MSI control registers control whether MSI generation is enabled and defines the address and data to be used for the MSI.
The entire example design is in the coreclkout_hip clock domain.
Note: The Intel L-/H-Tile Avalon-MM+ for PCI Express IP core does not include an internal DMA Controller. You can use the DMA Controller included in the example design that you can generate, or provide your own DMA Controller.