L-Tile and H-Tile Avalon® Memory-mapped+ Intel® FPGA IP for PCI Express* User Guide

ID 683527
Date 9/13/2024
Public
Document Table of Contents

6. Registers

The Intel L-/H-Tile Avalon-MM+ for PCI Express IP does not define any register in addition to the registers defined by the PCIe Hard IP and the PLLs.