E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs

ID 683468
Date 8/30/2022

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Document Table of Contents

2.11.13. Ethernet Link and Transceiver Signals

The E-Tile Hard IP for Ethernet Intel FPGA IP includes transceivers that implement two or four physical lanes at the line rates required for Ethernet channels.
Table 51.   Transceiver Signals
Note: n = number of channels.



o_tx_serial[n-1:0] (10GE/25GE)

o_tx_serial[3:0] (100GE)

TX transceiver data. Each o_tx_serial bit becomes two physical pins that form a differential pair.

i_rx_serial[n-1:0] (10GE/25GE)

i_rx_serial[3:0] (100GE)

RX transceiver data. Each i_rx_serial bit becomes two physical pins that form a differential pair.



The input clock i_clk_ref is the reference clock for the high-speed serial clocks.

This clock must have the same frequency as specified in PHY Reference Frequency parameter with a ±100 ppm accuracy per the IEEE 802.3-2015 Ethernet Standard.
This signal supports the following frequencies:
  • 156.25 MHz
  • 322.265625 MHz
  • 312.5 MHz
  • 644.53125 MHz

In addition, this clock must meet the jitter specification of the IEEE 802.3-2015 Ethernet Standard.

The PLL and clock generation logic use this reference clock to derive the transceiver and PCS clocks. The input clock should be a high quality signal on the appropriate dedicated clock pin. Refer to the Intel® Stratix® 10 Device Data Sheet or Intel® Agilex™ Device Data Sheet for transceiver reference clock phase noise specifications.

The index represents the number of reference clocks supported by this IP. The number is equivalent to the number of channels when refclk_mux is 0 with maximum value of 5 when refclk_mux is 1.
Note: By default, all channels are mapped to i_clk_ref[0] regardless of port's width or refclk_mux setting. For more information on how to change to a different reference clock, refer to the Switching Reference Clocks section in the E-Tile Transceiver PHY User Guide.


The o_tx_pll_locked[n-1:0] signal indicates when the transceiver PLL output clocks are locked.

The o_clk_pll_div64 and o_clk_pll_div66 clocks are reliable only after this signal bits are all high.