E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs

ID 683468
Date 8/30/2022

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Document Table of Contents Enable TX Pause Ports

Offset: 0x605

Enable TX Pause Ports Fields

Bit Name Description Access Reset
8:0 en_pfc_port Enable TX PAUSE or TX PFC port.

Bits [7:0]: For PFC

Bit [8]: For PAUSE

1: Corresponding tx_pfc_pause port can be used to trigger TX PFC frames
  • After power on, bit 8 defaults to 1
  • After i_csr_rst_n, the value of bit 8 is set based on the module parameter Stop TX traffic when link partner sends PAUSE?
RO 0x1