E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs

ID 683468
Date 8/30/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

3.10.9.1. CPRI PHY Reconfiguration Interface

Table 103.  CPRI PHY Reconfiguration Interface
Port Name Width Domain Description
i_sl_cpri_reconfig_addr[n] 19 bits per channel i_reconfig_clk Indicates address for the CPRI PHY Avalon-MM interface in a selected channel.
i_sl_cpri_reconfig_read[n] 1 bit per channel i_reconfig_clk Read command for the CPRI PHY Avalon-MM interface in a selected channel.
i_sl_cpri_reconfig_write[n] 1 bit per channel i_reconfig_clk Write command for the CPRI PHY Avalon-MM interface in a selected channel.
o_sl_cpri_reconfig_readdata[n] 32 bits per channel i_reconfig_clk Data read from the CPRI PHY Avalon-MM interface in a selected channel.
o_sl_cpri_reconfig_readdata_valid[n] 1 bit per channel i_reconfig_clk When the signal is high, it indicates that read data from CPRI PHY Avalon-MM interface is valid in a selected channel.
i_sl_cpri_reconfig_writedata[n] 32 bits per channel i_reconfig_clk Data write to the CPRI PHY Avalon-MM interface in a selected channel.
o_sl_cpri_reconfig_writerequest[n] 1 bit per channel i_reconfig_clk Avalon-MM stalling signal for operations on the CPRI PHY Avalon-MM interface in a selected channel.