E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs

ID 683468
Date 8/30/2022
Public

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3.8. Parameter Settings

You customize the IP core by specifying parameters in the IP parameter editor.
Table 88.  Parameter Settings: IP Tab
Parameter Supported Values Default Setting Description
CPRI Core Options
Number of CPRI Channels in core 1, 2, 3, 4 1 Sets the number of CPRI channels included in the CPRI core.
First RSFEC Lane
  • first_lane0
  • first_lane1
  • first_lane2
  • first_lane3
first_lane0 Sets the first RS-FEC lane.

This parameter is only available in IP core variations that target CPRI line rates with RS-FEC block.

RSFEC Clocking Mode
  • fec_dir_adp_clk_0
  • fec_dir_adp_clk_1
  • fec_dir_adp_clk_2
  • fec_dir_adp_clk_3
fec_dir_adp_clk_0 Sets the clocking mode for the RS-FEC block.

This parameter is only available in IP core variations that target CPRI line rates with RS-FEC block.

Configuration, Debug and Extension Options
Enable Native PHY Debug Master Endpoint
  • On
  • Off
On

When you turn on this parameter, the Native PHY Debug Master Endpoint instantiates an Avalon® -MM master and connects the Avalon-MM slave inside the PHY. This allows access to the PHY registers for debug using the Intel Transceiver Toolkit via JTAG.

Table 89.  Parameter Settings: CPRI Channel(s) Tab
Parameter Supported Values Default Setting Description
CPRI General Options
CPRI Rate
  • 2.4376G (8b/10b)
  • 3.072G (8b/10b)
  • 4.9152G (8b/10b)
  • 6.144G (8b/10b)
  • 9.8304G (8b/10b)
  • 10.1376G (64b/66b)
  • 10.1376G (64b/66b) with RSFEC
  • 12.16512G (64b/66b)
  • 12.16512G (64b/66b) with RSFEC
  • 24.33024G (64b/66b)
  • 24.33024G (64b/66b) with RSFEC
10.1376G (64b/66b) Selects the CPRI data rate.

The hard RS-FEC block is included in the core if you select 10.1376, 12.1651, and 24.33024 Gbps (64b/66b) with the RS-FEC option.

Enable reconfiguration to 8b/10b datapath
  • On
  • Off
Off Turn on this parameter if you plan to reconfigure the CPRI line rate of your channels from 64b/66b datapath rates to 8b/10b datapath rates at run-time.

If this option is not enabled, the CPRI IP core uses fewer resources, and not be able to change to 8b/10b datapath rates at run-time.

CPRI PMA Options
PHY Reference frequency
  • 153.6 MHz
  • 184.32 MHz
184.32 MHz Support this value of the reference clock frequency for each CPRI line rate.

The CPRI line rates that include 8b/10b soft PCS use a reference clock of 153.6 MHz and the CPRI line rates that include 64b/66b hard PCS use a reference clock of 184.32 MHz.

This option is grayed out and always disabled in the current version of the Intel® Quartus® Prime software.

For parameters in the PMA Adaptation tab, refer to the PMA Adaptation topic in the E-Tile Transceiver PHY User Guide.

For parameters in the Example Design tab, refer to the device specific E-tile Hard IP Intel® Stratix® 10 Design Examples User Guides, or E-tile Hard IP Intel® Agilex™ Design Examples User Guides.

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