E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs

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ID 683468
Date 8/30/2022
Public
Document Table of Contents

2.12.2.38. BIP Counter 10

Offset: 0x36B

BIP Counter 10 Fields

Bit Name Description Access Reset
15:0 count BIP Counter
Shows current BIP count for corresponding PCS lane.
  • Used only for multilane Ethernet links
  • Increments for a given virtual lane when the BIP calculated over all the data received since the last alignment marker does not match the BIP value in the current Alignment Marker
  • Valid only after Alignment Marker lock
  • Rolls over at max count (2^16 BIP errors)
  • Can be captured by snapshot or RX Shadow request
  • Resets on RX datapath reset (i_rx_rst_n)
  • RX Stats Reset CSR does not reset this counter
RO 0x0

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