E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs
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Visible to Intel only — GUID: ipg1520913441515
Ixiasoft
Visible to Intel only — GUID: ipg1520913441515
Ixiasoft
2.12.2.4. PHY Configuration
Offset: 0x310
PHY Configuration Fields
Bit | Name | Description | Access | Reset |
---|---|---|---|---|
5 | set_data_lock | Set data lock 1: Force PLL to lock to data |
RW | 0x0 |
4 | set_ref_lock | Set ref lock 1: Force PLL to lock to reference |
RW | 0x0 |
2 | soft_rx_rst | Soft RXP Reset 1: Resets the RX PCS and RX MAC. |
RW | 0x0 |
1 | soft_tx_rst | Soft TXP Reset 1: Resets the TX PCS and TX MAC. |
RW | 0x0 |
0 | eio_sys_rst | Ethernet IO System Reset 1: Resets the IP core (TX and RX MACs, Ethernet reconfiguration registers, PCS, and transceivers). |
RW | 0x0 |