E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs

ID 683468
Date 8/30/2022
Public

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3.11.2. CPRI PHY Registers

These registers use 32-bit addresses; they are not byte-addressable.
Table 108.  CPRI PHY Registers
Address Bit Name Description Access Reset
0xC00 31:10 Reserved
9:5 rx_bitslipboundary_sel Reports the number of bits the 8B/10B RX PCS block slipped to achieve a deterministic latency. RO 0x0
4 cpri_fec_en Indicates whether the RS-FEC block is enabled. Deterministic latency uses this register.
  • 0: Disable RS-FEC
  • 1: Enable RS-FEC

You must reset TX and RX datapaths after changing this bit.

RW The reset value depends on the selected IP variant. For example, the reset value is 1 if the instantiated IP variant is 24.33024G (64/66b) with RS-FEC.
3:0 cpri_rate_sel Selects the CPRI speed. EFIFO and deterministic latency use this register.
  • 0x2: 2.4 Gbps
  • 0x3: 3 Gbps
  • 0x4: 4.9 Gbps
  • 0x5: 6.1 Gbps
  • 0x6: 9.8 Gbps
  • 0x9: 10.1 Gbps
  • 0xA: 12.1 Gbps
  • 0xB: 24.3 Gbps

You must reset TX and RX datapaths after changing this bit.

RW The reset value depends on the selected IP variant. For example, the reset value is 0xB if the instantiated IP variant is 24.33024G (64/66b) with RS-FEC.
0xC01 31:2 Reserved
1 dl_master_reset Indicates the master reset that allows deterministic latency (DL) measurement to be retaken:
  • 0: Reset disabled
  • 1: Reset enabled
RW 0x1
0 measure_valid Indicates whether the deterministic values are valid
  • 0: Invalid
  • 1: Valid
RO 0x0
0xC02 31:21 Reserved
20:0 tx_delay Indicates deterministic latency measurement values for TX data path latency in fixed format (Q13.8).

This value is valid only if measure_valid = 1.

RO 0x0
0xC03 31:21 Reserved
20:0 rx_delay Indicates deterministic latency measurement values for RX data path latency in fixed format (Q13.8).

This value is valid only if measure_valid = 1.

RO 0x0
0xC04- 0xC0F 31:0 Reserved

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