E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs

ID 683468
Date 8/30/2022

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

3.3. E-Tile CPRI PHY Device Family Support

Table 81.   Intel® FPGA IP Core Device Support Levels

Device Support Level



The IP core is available for simulation and compilation for this device family. Timing models include initial engineering estimates of delays based on early post-layout information. The timing models are subject to change as silicon testing improves the correlation between the actual silicon and the timing models. You can use this IP core for system architecture and resource utilization studies, simulation, pinout, system latency assessments, basic timing assessments (pipeline budgeting), and I/O transfer strategy (datapath width, burst depth, I/O standards tradeoffs).


The IP core is verified with preliminary timing models for this device family. The IP core meets all functional requirements, but might still be undergoing timing analysis for the device family. It can be used in production designs with caution.


The IP core is verified with final timing models for this device family. The IP core meets all functional and timing requirements for the device family and can be used in production designs.

Table 82.   E-Tile CPRI PHY IP Core Device Family SupportShows the level of support offered by the E-Tile CPRI PHY IP core for each Intel® FPGA device family.

Device Family


Intel® Stratix® 10

E-tile devices only


Intel® Agilex™

E-tile devices only


Other device families

No support