E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs

ID 683468
Date 8/30/2022
Public

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2.7.4.2. Pin Assignments

When you integrate your E-Tile Hard IP for Ethernet Intel FPGA IP core instance in your design, you must make appropriate pin assignments. You can create a virtual pin to avoid making specific pin assignments for top-level signals until you are ready to map the design to hardware.

Intel® Stratix® 10 E-tile devices offer four instances of the hard IP on each E-tile. Each instance offers one 100G channel and six 10G/25G channels. Your design must not include pin assignments that conflict with its location. In devices with multiple E-tiles, you can specify the E-tile to which the Ethernet link serial pins should map.

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