E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs

ID 683468
Date 8/30/2022

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Document Table of Contents PTP Transmit Functionality

When you send a 1588 PTP packet to a E-Tile Hard IP for Ethernet Intel FPGA IP with Enable IEEE 1588 PTP turned on in the parameter editor, you must assert one and only one of the following input signals with the TX SOP signal to tell the IP core the incoming packet is a 1588 PTP packet:

  • i_sl_ptp_ts_req/i_ptp_ts_req : assert this signal to tell the IP core to process the current packet in two-step processing mode.
  • i_sl_ptp_ins_ets/i_ptp_ins_ets: assert this signal to tell the IP core to process the current packet in one-step processing mode and to insert the exit timestamp for the packet in the packet (insertion mode).
  • i_sl_ptp_ins_cf/i_ptp_ins_cf: assert this signal to tell the IP core to process the current packet in one-step processing mode and to update the timestamp in the packet by adding the latency through the IP core (the residence time in the IP core) to the cumulative delay field maintained in the packet (correction mode). This mode supports transparent clock systems.
Note: For 100G variant, these signal names are sightly different. Refer to the 1588 PTP Interface for signal name details.

All TX PTP operations assume the o_sl_tx_ptp_ready signal was asserted and is held high.

Figure 24. Example Waveform for 2-step TX Timestamp using i_sl_ptp_ts_req Signal
Figure 25. Example Waveform for 1-step TX Timestamp using i_sl_ptp_ins_ets Signal
Figure 26. Example Waveform for 1-step TX Timestamp using i_sl_ptp_ins_cf Signal

The IP core transmits the 1588 PTP packet in an Ethernet frame after PTP processing.

Figure 27. PTP Transmit Block Diagram

In one-step mode, the IP core either overwrites the timestamp information provided at the user-specified offset with the packet exit timestamp (insertion mode), or adds the residence time in this system to the value at the specified offset (correction mode). You tell the IP core how to process the timestamp by asserting the appropriate signal with the TX SOP signal. You must specify the offset of the timestamp in the packet (i_ptp_ts_offset) in insertion mode, or the offset of the correction field in the packet (i_ptp_cf_offset) in correction mode. In addition, the IP core zeroes out or updates the UDP checksum, or leaves the UDP checksum as is, depending on the mutually exclusive i_ptp_zero_csum and i_ptp_update_eb signals.

Note: If the PTP packet resides in the system for more than 4 seconds, the correction field shows a mismatched value with a very large number.

Two-step PTP processing ignores the values on the one-step processing signals. In two-step processing mode, the IP core does not modify the current timestamp in the packet. Instead, the IP core transmits a two-step derived timestamp on the separate o_ptp_ets[95:0] bus, when it begins transmitting the Ethernet frame. The value on the o_ptp_ets bus is the packet exit timestamp. The o_ptp_ets bus holds a valid value when the corresponding o_ptp_ets_valid signal is asserted.

In addition, to help the client to identify the packet, you can specify a fingerprint to be passed by the IP core in the same clock cycle with the timestamp. The E-Tile Hard IP for Ethernet Intel FPGA IP has a fixed 8 bit width for fingerprint. You provide the fingerprint value to the IP core in the i_ptp_fp signal. The IP core then drives the fingerprint on the appropriate o_ptp_ets_fp port with the corresponding output timestamp, when it asserts the o_ptp_ets_valid signal.

The IP core calculates the packet exit timestamp using reference block timing. The egress time of blocks which marked as references, are measured directly at the serializer, and are used to calculate the egress times of all other bits.

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