E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs

ID 683468
Date 8/30/2022
Public

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2.12.4.3. Maximum RX Frame Size

Offset: 0x506

Maximum RX Frame Size Fields

Bit Name Description Access Reset
15:0 max_rx MAX_RX_SIZE_CONFIG

16b value that sets the maximum RX frame size. When RX frames exceed this size, the CNTR_RX_OVERSIZE statistic is incremented, and the appropriate rx_error bit is asserted with EOP on the frame to indicate the frame is oversize

Sets the maximum size of a RX frame in octets before it can be counted as an oversize frame
  • When enforce_max_frame_size is enabled, frames longer than max_rx can be truncated on arrival, and marked as oversize, with an FCS error
  • After power-up, max_rx is set to 16'd9600
  • After i_csr_rst_n, max_rx is set to the value given by the module parameter RX maximum frame size
RW 0x2580

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