E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs

ID 683468
Date 8/30/2022

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents Clock Requirements

The E-Tile Hard IP for Ethernet Intel FPGA IP provides locally generated PLL clocks used for RX and TX datapath, and recovered clocks to enable Synchronous Ethernet (SyncE).

For synchronized-mode operation without external AIB clocking enabled, ensure that the output clock, o_clk_pll_div64, drives both i_sl_clk_rx and the i_sl_clk_tx input clocks. If multiple IP core instances are instantiated, connect o_clk_pll_div64 output clock of respective channel to its input clocks. When external AIB clocking is enabled, i_sl_clk_tx and i_sl_clk_rx input clocks must be driven by the same source as i_aib_clk. Another important aspect for Synchronous Ethernet operation is to connect filtered and divided version of RX recovered clock (o_clk_rec_div64 or o_clk_rec_div66) to input reference clock (i_clk_ref).

For any PTP variants, Intel recommends using the clock output from PTP channel adjacent to the data channel. For example, in a three-channel 25G design for EHIP_CORE0/2, your design must use the clock output from the PTP channel adjacent to channel 3. Similarly, for EHIP_CORE1/3, use clock output from the PTP channel next to channel 0.