E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs
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Visible to Intel only — GUID: ewe1520913474320
Ixiasoft
Visible to Intel only — GUID: ewe1520913474320
Ixiasoft
2.12.2.17. PCS Virtual Lane 0
Offset: 0x330
PCS Virtual Lane 0 Fields
Bit | Name | Description | Access | Reset |
---|---|---|---|---|
29:25 | vlane5 | Virtual lane mapping Original virtual lane position of the data mapped to the PCS lane with this index. For example, if you read the value 5 from vlane 12, it means the virtual lane data that the link partner transmitted on virtual lane 5 is being received on virtual lane 12. EHIP reorders the data automatically |
RO | 0x1F |
24:20 | vlane4 | |||
19:15 | vlane3 | |||
14:10 | vlane2 | |||
9:5 | vlane1 | |||
4:0 | vlane0 |