E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs

ID 683468
Date 8/30/2022
Public

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2.11.17.3.10. Multiple 25G Synchronous Ethernet Channels

For multi-channel synchronous Ethernet configuration, one TX eFIFO is instantiated for each Ethernet channel when Enable SyncE is enabled. The write data valid signal of the FIFO is connected internally to the custom cadence port of hard IP.

Similar to single channel configuration, RX recovered clock of each channel is fed to on-board clock cleaner for jitter removal. The clock cleaner should filter and generate the correct frequency for i_clk_ref input reference clock. After power up, the clock cleaner has to provide default reference clock before RX recovered clock is available at o_clk_rec_div64/66.

There are two ways to connect filtered and divided RX recovered clock to i_clk_ref:
  1. Dedicated reference clock: Recovered clock from each channel is fed to input reference clock of respective channel. For example, connect filtered RX clock from Channel 0 to i_clk_ref of Channel 0, filtered RX clock from Channel 1 to i_clk_ref of Channel 1. Parameter Enable SyncE must be enabled to support this method.
  2. Common reference clock: Only one of the RX recovered clocks to be connected to input reference clock of all channels. For example, connect filtered RX clock from Channel 0 to i_clk_ref of Channel 0 and Channel 1. Make sure that all channels have the same input reference clock frequency.
Figure 69. 25G x4 (FEC On) SyncE Without External AIB Clocking
Figure 70. 25G x4 (FEC On) SyncE With External AIB Clocking, Dedicated Reference Clock
Figure 71. 25G x4 (FEC On) SyncE With External AIB Clocking, Shared Reference Clock

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