E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs

ID 683468
Date 8/30/2022
Public

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2.11.17.2. Asynchronous Adapter Clock in 100G Mode

When Enable asynchronous adapter clocks is enabled, i_clk_rx and i_clk_tx can be asynchronous from each other and from o_clk_pll_div64 clock as long as the clocks are fast enough to ensure all data is processed by a channel.

Note: For 100G mode, the asynchronous adapter clocks are only available when PTP is disabled.
Figure 57. Clock Connection in Asynchronous FIFO Operation

Below table summarizes minimum and maximum frequencies required for i_clk_rx and i_clk_tx during the Asynchronous mode.

Table 61.  Supported Clock Rates for MAC Client Asynchronous FIFO Operation in 100G ModeThe below rates assume 1 byte IPG and disabled preamble-pass-through.
Rate Clock Rate
Min i_clk_tx Max i_clk_tx Min i_clk_rx Max i_clk_rx

100G

340 MHz

420 MHz

340 MHz + 200 ppm

420 MHz + 200 ppm

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