E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs

ID 683468
Date 8/30/2022

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Document Table of Contents Auto Negotiation Config Register 5

Offset: 0xC5

Auto Negotiation Config Register Fields

Bit Name Description Access Reset
30:16 override_an_tech_22_8 AN_TECH Override Value, bits [22:8]

When Override AN Parameters is enabled (override_an_parameters_enable=1), this register controls the lower bits of AN_TECH used in the AN Base page.

[16] = 100GBASE-CR4

[17] = 25GBASE-KR-S/CR-S

[18] = 25GBASE-KR/CR

[19] = 2.5GBASE-KX

[20] = 5GBASE-KR

[21] = 50GBASE-KR/CR

[22] = 100GBASE-KR2/CR2

[23] = 200GBASE-KR4/CR4

All other settings Reserved

RW 0x0
15:0 user_next_page_low User Controlled AN Next Page (lower bits)

The AN TX state machine uses these bits when user controlled Next Page is set (an_next_pages_ctrl=1).

[15]: Next Page bit

[14]: ACK bit (controlled by the state machine)

[13]: MP bit

[12]: ACK2 bits

[11]: Toggle bit (controlled by the state machine)

[10:0]: Message code field [10:0]/Unformatted code field[10:0]

Note: When Consortium Next Page send is enabled (consortium_next_page_send=1), the Consortium Next Page sequence is sent after the last user Next Page.
RW 0x0