E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs

ID 683468
Date 8/30/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

3.1. Supported Features

The E-Tile CPRI PHY Intel FPGA IP core has the following features:
  • Compliant with the CPRI Specification V7.0 (2015-10-09)
  • Supports up to 23 CPRI channels
  • Supports configurable CPRI communication line bit rate of 2.4376, 3.0720, 4.9152, 6.1440, 9.8304, 10.1376, 12.1651 and 24.33024 Gbps using Intel® Stratix® 10 and Intel® Agilex™ E-tile transceivers
  • Supports dynamic reconfiguration to different line bit rates during run time
  • Supports RS-FEC block for 10.1376, 12.1651 and 24.33024 Gbps line bit rate
  • Supports deterministic latency measurement
  • Provides register access interface to external or on-chip processor, using the Intel® Avalon® Memory-Mapped ( Avalon® -MM) interconnect specification
  • Supports Physical Medium Attachment (PMA) adaptation
Table 80.   E-Tile CPRI PHY IP Core Feature MatrixThe Intel® Quartus® Prime Pro Edition software supports the following combinations
CPRI Line Bit Rate (Gbps) RS-FEC Support Reference Clock (MHz) Deterministic Latency Support
2.4376 No 153.6 Yes
3.0720 No 153.6 Yes
4.9152 No 153.6 Yes
6.1440 No 153.6 Yes
9.8304 No 153.6 Yes
10.1376 With and Without 184.32 Yes
12.1651 With and Without 184.32 Yes
24.33024 With and Without 184.32 Yes

Did you find the information on this page useful?

Characters remaining:

Feedback Message