E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs

ID 683468
Date 8/30/2022
Public

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Document Table of Contents

2.12.2.8. Frame Errors Detected

Offset: 0x323

Frame Errors Detected Fields

Bit Name Description Access Reset
19:0 frmerr Frame error(s) detected
  • 1: A frame error was detected on corresponding lane
  • For single lanes, only bit 0 is used
  • For 100G links, bits 19:0 are used, corresponding to Virtual lanes 0 to 19
  • This bit is sticky, and must be cleared by asserting sclr_frame_error
RO 0x0

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