E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs

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ID 683468
Date 8/30/2022
Public
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3.11.3.1. Minimizing PMA Adaptation Time

When you change the line bit rate of the E-Tile CPRI PHY Intel FPGA IP, you need to calibrate the PMA to obtain the optimal performance. After you initiate a rate switch, the E-Tile CPRI PHY IP requires 100 ms for PMA to be ready. To meet this requirement, you need to minimize the PMA adaptation time by configuring the PMA adaptive engine to use adaptation presets through the PMA registers.

Select the PMA parameter by setting the PMA attribute code 0x2C to PMA attribute value 0x118 into the PMA attribute code registers.

  1. Write 0x84[7:0] = 0x18.
  2. Write 0x85[7:0] = 0x1.
  3. Write 0x86[7:0] = 0x2C.
  4. Write 0x87[7:0] = 0x0.
  5. Write 0x90[0] = 1'b1.
  6. Read 0x8A[7]. It should be 1.
  7. Read 0x8B[0], until it changes to 0.
  8. Write 0x8A[7] to 1 to clear the 0x8A[7] flag.

Write a value to the PMA parameter by setting the PMA attribute code 0x6C to PMA attribute value 0x0 into the PMA attribute code registers.

  1. Write 0x84[7:0] = 0x0.
  2. Write 0x85[7:0] = 0x00.
  3. Write 0x86[7:0] = 0x6C.
  4. Write 0x87[7:0] = 0x00.
  5. Write 0x90[0] = 1'b1.
  6. Read 0x8A[7]. It should be 1.
  7. Read 0x8B[0], until it changes to 0.
  8. Write 0x8A[7] to 1 to clear the 0x8A[7] flag.

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