E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs

ID 683468
Date 8/30/2022
Public

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2.7.5. IP Core Testbenches

Intel provides a compilation-only design example and a testbench that you can generate for the E-Tile Hard IP for Ethernet Intel FPGA IP.

To generate the testbench, in the E-Tile Hard IP for Ethernet Intel FPGA IP parameter editor, you must first set the parameter values for the IP core variation you intend to generate in your end product. If you do not set the parameter values for your DUT to match the parameter values in your end product, the testbench you generate does not exercise the IP core variation you intend.

The testbench demonstrates a basic test of the IP core. It is not intended to be a substitute for a full verification environment.

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