E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs

ID 683468
Date 8/30/2022

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Document Table of Contents PFC Holdoff Quanta 7

Offset: 0x62F

PFC Holdoff Quanta 7 Fields

Bit Name Description Access Reset
15:0 holdoff_quanta PFC Holdoff Quanta
16b value specifying holdoff time before another XOFF is transmitted when the corresponding Enable Automatic TX Pause Retransmission register bit is 1
  • Times are programmed in holdoff quanta
    • For 10G and 25G links, 1 Holdoff Quanta = 8 clock cycles
    • For 100G links, 1 Holdoff Quanta = 2 clock cycles
  • Min value is 1, but to minimize wasted bandwidth, holdoff should be set as large as possible without exceeding the recommended max value
  • Max value for correct operation where holdoff retransmits PFC requests before the previously transmitted Quanta expires is:
    • For 10G and 25G links: corresponding pause/pfc quanta - (60 + Maximum TX Frame Size register value/8)
      • For example, if the corresponding pause quanta is 1000, and the max tx frame size is 880 bytes, the max holdoff quanta is 1000-(60+110) = 830
      • These values are based on the max overrun limits defined in IEEE 802.3 2015 Annex 31B
    • For 100Gx4 links: corresponding pause/pfc quanta - (50 + Maximum TX Frame Size register value/32)
  • After power-on, holdoff_quanta defaults to 16'hFFFF
  • After i_cfg_rst_n, holdoff_quanta defaults to the value in the module parameter holdoff_quanta for pause, and pfc_holdoff_quanta_n for PFC