22.214.171.124. Logic Lock Regions Requirements for PTP Accuracy Advanced Mode
- In Intel® Quartus® Prime Pro Edition software, run the initial compilation to place channels in the required location.
- In the command line, execute the alt_ehipc3_10g25g_ptp_advancedmode_logiclockreg_gen.tcl script with the following command:
quartus_sta -t alt_ehipc3_10g25g_ptp_advancedmode_logiclockreg_gen.tcl -project <project name> [-revision <revision name>] [-file <output file name>]Note: The project name is a required field. The revision name is an optional field.
- Re-run the compilation step to compile the design with added logic lock regions .qsf assignments.
Whenever you perform additional design change or design optimization, you only need to execute step 3. If you change the channel placement or select a different E-tile, you must delete previously generated logic lock regions and execute steps 1 through 3 to regenerate the logic lock regions with the new channel location.
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