E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs

ID 683468
Date 8/30/2022

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents Enable Uniform Holdoff

Offset: 0x60B

Enable Uniform Holdoff Fields

Bit Name Description Access Reset
0 en_holdoff_all Enable uniform holdoff
All queues must use a holdoff at least as long as the holdoff programmed into Set Uniform Holdoff register.
  • At power up this register defaults to 0
  • After i_csr_rst_n is asserted, this register value is set according to the module parameter flow_control_holdoff_mode
RW 0x0