E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs

ID 683468
Date 8/30/2022

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Document Table of Contents Soft Reset Sequencer

The soft reset sequencer block manages the digital reset sequence in the soft logic of the E-Tile CPRI PHY IP.

Figure 85. Conceptual Overview of General IP Core Reset Logic
The IP has four input reset signals and three reset registers. The following table shows the functionality of each reset port and register.
Table 90.  Reset Signal and Register FunctionsIn this table, a tick (√) indicates the block is reset by the specified reset signal. A dash (—) indicates the block is not impacted by the specified reset signal.
Reset Port/Register Block
TX EMIB Interface TX PCS TX PMA Interface RX EMIB Interface RX PCS RX PMA Interfaces Hard CSR Soft CSR











Reset Sequence

The following waveforms show the reset sequence using the i_sl_csr_rst_n, i_sl_tx_rst_n, and i_sl_rx_rst_n signals.

System Considerations

You should perform a system reset before beginning IP core operation, preferably by asserting the i_csr_rst_n and i_reconfig_reset signals together. The IP core implements the correct reset sequence to reset the entire IP core.

If you assert the transmit reset when the downstream receiver is already aligned, the receiver loses alignment. Before the downstream receiver loses lock, it might receive some malformed frames.

If you assert the receive reset while the upstream transmitter is sending packets, the packets in transit get corrupted.

Figure 86. External Hard Reset Sequence
Figure 87. TX Datapath Reset Sequence
Figure 88. RX Datapath Reset Sequence

For the CPRI data rates with RS-FEC variant, deasserting the master channel's the i_sl_csr_rst_n signal interrupts all slave channels.

35 Reset a subset of the PMA functions.
36 soft_sys_rst resets only the registers in the hard logic and returns the register values to the original SOF values.

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