E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs

ID 683468
Date 8/30/2022
Public

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2.11.14.3. RS-FEC Reconfiguration Interfaces

You access RS-FEC control and status registers of the E-Tile Hard IP for Ethernet Intel FPGA IP during normal operation using an Avalon® -MM interface.
Table 54.  RS-FEC Reconfiguration InterfaceThe signals in this interface are clocked by the i_reconfig_clk clock and reset by i_reconfig_reset.
Port Name Width Description

i_rsfec_reconfig_addr

11

Address bus for RS-FEC control and status registers in the respective channel.

i_rsfec_reconfig_write

1

Write request signal for RS-FEC control and status registers in the respective channel.

i_rsfec_reconfig_read

1

Read request signal for RS-FEC control and status registers in the respective channel.

i_rsfec_reconfig_writedata

8

Write data for RS-FEC control and status registers in the respective channel.

o_rsfec_reconfig_readdata 8

Read data from reads to RS-FEC control and status registers in the respective channel.

o_rsfec_reconfig_waitrequest 1

Avalon-MM stalling signal for operations on RS-FEC control and status registers in the respective channel.

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