Intel Stratix 10 Device Datasheet
Intel Stratix 10 Device Datasheet
Device Grade | Speed Grade Supported |
---|---|
Extended |
|
Industrial |
|
Commercial |
|
The suffix after the speed grade denotes the power options offered in Intel® Stratix® 10 devices.
- V—SmartVID with standard static power. For “V” suffix devices, both VCC and VCCP must share the same SmartVID regulator. VCCL_HPS can share the same SmartVID regulator or can use a separate fixed voltage regulator.
- L—0.85 V fixed voltage with low static power
- X—0.85 V fixed voltage with lowest static power
Variant | Datasheet Status |
---|---|
Intel® Stratix® 10 GX | Final (Preliminary for 1SG040HF35 device only) |
Intel® Stratix® 10 SX | Final (Preliminary for 1SX040HF35 device only) |
Intel® Stratix® 10 TX | Final |
Intel® Stratix® 10 MX | Final |
Intel® Stratix® 10 DX | Final 1 |
Electrical Characteristics
The following sections describe the operating conditions and power consumption of Intel® Stratix® 10 devices.
Operating Conditions
Intel® Stratix® 10 devices are rated according to a set of defined parameters. To maintain the highest possible performance and reliability of the Intel® Stratix® 10 devices, you must consider the operating requirements described in this section.
Absolute Maximum Ratings
This section defines the maximum operating conditions for Intel® Stratix® 10 devices. The values are based on experiments conducted with the devices and theoretical modeling of breakdown and damage mechanisms. The functional operation of the device is not implied for these conditions.
Symbol | Description | Condition | Minimum | Maximum | Unit |
---|---|---|---|---|---|
VCC | Core voltage power supply | — | –0.50 | 1.26 | V |
VCCP | Periphery circuitry and transceiver fabric interface power supply | — | –0.50 | 1.26 | V |
VCCERAM | Embedded memory and digital transceiver power supply | — | –0.50 | 1.24 | V |
VCCPT | Power supply for programmable regulator and I/O pre-driver | — | –0.50 | 2.46 | V |
VCCBAT | Battery back-up power supply for design security volatile key register | — | –0.50 | 2.46 | V |
VCCIO_SDM | Configuration pins power supply | — | –0.50 | 2.19 | V |
VCCIO | I/O buffers power supply (except for 1SG040HF35 and 1SX040HF35 banks 3C and 3D) | 3 V I/O | –0.50 | 4.10 | V |
LVDS I/O 2 | –0.50 | 2.19 | V | ||
VCCIO3C | I/O buffers power supply for 1SG040HF35 and 1SX040HF35 devices bank 3C only | — | –0.50 | 3.63 | V |
VCCIO3D | I/O buffers power supply for 1SG040HF35 and 1SX040HF35 devices bank 3D only | — | –0.50 | 1.98 | V |
VCCA_PLL | Phase-locked loop (PLL) analog power supply | — | –0.50 | 2.46 | V |
VCCPLLDIG_SDM | Secure Device Manager (SDM) block PLL digital power supply | — | –0.50 | 1.21 | V |
VCCPLL_SDM | SDM block PLL analog power supply | — | –0.50 | 2.19 | V |
VCCFUSEWR_SDM | Fuse block writing power supply | — | –0.50 | 3.19 | V |
VCCADC | ADC voltage sensor power supply | — | –0.50 | 2.19 | V |
VCCIO_UIB | Power supply for the Universal Interface Bus between the core and embedded HBM2 memory | — | –0.30 | 1.50 | V |
VCCM_WORD | Power supply for the embedded HBM2 memory | — | –0.30 | 3.00 | V |
VCCT_GXB | Transmitter analog power supply | — | –0.50 | 1.47 | V |
VCCR_GXB | Receiver analog power supply | — | –0.50 | 1.47 | V |
VCCH_GXB | Transmitter output buffer power supply | — | –0.50 | 2.46 | V |
VCCRT_GXE | E-tile transceiver power supply | — | –0.50 | 1.21 | V |
VCCRTPLL_GXE | E-tile transceiver PLL power supply | — | –0.50 | 1.21 | V |
VCCH_GXE | E-tile transceiver analog power supply | — | –0.50 | 1.47 | V |
VCCCLK_GXE | E-tile transceiver LVPECL REFCLK power supply | — | –0.50 | 3.41 | V |
VCCRT_GXP | P-tile transceiver power supply | — | –0.50 | 1.21 | V |
VCCFUSE_GXP | P-tile transceiver eFuse power supply | — | –0.50 | 1.21 | V |
VCCH_GXP | P-tile transceiver analog power supply | — | –0.50 | 2.46 | V |
VCCCLK_GXP | P-tile transceiver I/O buffer power supply | — | –0.50 | 2.46 | V |
VCCL_HPS | HPS core voltage and periphery circuitry power supply | — | –0.50 | 1.30 | V |
VCCIO_HPS | HPS I/O buffers power supply | LVDS I/O 2 | –0.50 | 2.19 | V |
VCCPLL_HPS | HPS PLL power supply | — | –0.50 | 2.46 | V |
VI | DC input voltage | 3.3 V I/O | –0.30 | VCCIO + 0.33 | V |
3 V I/O | –0.30 | VCCIO + 0.65 | V | ||
LVDS I/O | –0.30 | VCCIO + 0.3 | V | ||
IOUT | DC output current per pin | — | –15 3 4 5 6 7 | 15 | mA |
TJ | Absolute junction temperature for Intel® Stratix® 10 MX, NX, and DX 2100 devices | — | –55 | 120 | °C |
Absolute junction temperature for Intel® Stratix® 10 GX 10M device | — | 0 | 125 | °C | |
Absolute junction temperature for all other Intel® Stratix® 10 devices | — | –55 | 125 | °C | |
TSTG | Storage temperature (no bias) for Intel® Stratix® 10 MX, NX, and DX 2100 devices | — | –55 | 120 | °C |
Storage temperature (no bias) for Intel® Stratix® 10 GX 10M device | — | 0 | 125 | °C | |
Storage temperature (no bias) for all other Intel® Stratix® 10 devices | — | –55 | 150 | °C |
Maximum Allowed Overshoot and Undershoot Voltage
During transitions, input signals may overshoot to the voltage listed in the following table and undershoot to –1.1 V for input currents less than 100 mA and periods shorter than 20 ns.
The maximum allowed overshoot duration is specified as a percentage of high time over the lifetime of the device. A DC signal is equivalent to 100% duty cycle.
For example, when using VCCIO = 1.8 V, a signal that overshoots to 2.44 V for LVDS I/O can only be at 2.44 V for ~6% over the lifetime of the device.
Symbol | Description | LVDS I/O (V) 8 | Overshoot Duration as % at TJ = 100°C | Unit |
---|---|---|---|---|
Vi (AC) | AC input voltage | VCCIO + 0.30 | 100 | % |
VCCIO + 0.35 | 60 | % | ||
VCCIO + 0.40 | 30 | % | ||
VCCIO + 0.45 | 20 | % | ||
VCCIO + 0.50 | 10 | % | ||
VCCIO + 0.55 | 6 | % | ||
> VCCIO + 0.55 | No overshoot allowed | — |
Symbol | Description | 3 V I/O (V) | Overshoot Duration as % at TJ = 100°C | Unit |
---|---|---|---|---|
Vi (AC) | AC input voltage | VCCIO + 0.65 | 100 | % |
VCCIO + 0.70 | 42 | % | ||
VCCIO + 0.75 | 18 | % | ||
VCCIO + 0.80 | 9 | % | ||
VCCIO + 0.85 | 4 | % | ||
> VCCIO + 0.85 | No overshoot allowed | — |
Symbol | Description | 3.3 V I/O (V) | Overshoot Duration as % at TJ = 100°C | Unit |
---|---|---|---|---|
Vi (AC) | AC input voltage | VCCIO + 0.33 | 100 | % |
VCCIO + 0.41 | 60 | % | ||
VCCIO + 0.47 | 40 | % | ||
VCCIO + 0.69 | 10 | % | ||
VCCIO + 0.95 | 2 | % | ||
> VCCIO + 0.95 | No overshoot allowed | — |
For an overshoot of 2.5 V, the percentage of high time for the overshoot can be as high as 100% over a 10-year period. Percentage of high time is calculated as ([delta T]/T) × 100. This 10-year period assumes that the device is always turned on with 100% I/O toggle rate and 50% duty cycle signal.
Recommended Operating Conditions
This section lists the functional operation limits for the AC and DC parameters for Intel® Stratix® 10 devices.
Recommended Operating Conditions
Symbol | Description | Condition | Minimum 9 | Typical | Maximum 9 | Unit |
---|---|---|---|---|---|---|
VCC | Core voltage power supply for Intel® Stratix® 10 GX 10M device | –E2L, –C2L | 0.85 | 0.88 | 0.91 | V |
Core voltage power supply for all other Intel® Stratix® 10 devices | –E1V, –I1V, –E2V, –I2V, –E3V, –I3V 10 | (Typical) – 30 mV | 0.8 – 0.94 | (Typical) + 30 mV | V | |
–E2L, –I2L, –E3X, –I3X | 0.82 | 0.85 | 0.88 | V | ||
VCCP | Periphery circuitry and transceiver fabric interface power supply for Intel® Stratix® 10 GX 10M device | –E2L, –C2L | 0.85 | 0.88 | 0.91 | V |
Periphery circuitry and transceiver fabric interface power supply for all other Intel® Stratix® 10 devices | –E1V, –I1V, –E2V, –I2V, –E3V, –I3V 10 | (Typical) – 30 mV | 0.8 – 0.94 | (Typical) + 30 mV | V | |
–E2L, –I2L, –E3X, –I3X | 0.82 | 0.85 | 0.88 | V | ||
VCCIO_SDM | Configuration pins power supply | 1.8 V | 1.71 | 1.8 | 1.89 | V |
VCCPLLDIG_SDM | Secure Device Manager (SDM) block PLL digital power supply | — | 0.87 | 0.9 | 0.93 | V |
VCCPLL_SDM | SDM block PLL analog power supply | — | 1.71 | 1.8 | 1.89 | V |
VCCFUSEWR_SDM | Fuse block writing power supply | — | 2.35 | 2.4 | 2.45 | V |
VCCADC | ADC voltage sensor power supply | — | 1.71 | 1.8 | 1.89 | V |
VCCERAM | Embedded memory and digital transceiver power supply | 0.9 V | 0.87 | 0.9 | 0.93 | V |
VCCBAT 11 | Battery back-up power supply (For design security volatile key register) | — | 1.2 | — | 1.8 | V |
VCCPT | Power supply for programmable regulator and I/O pre-driver | 1.8 V | 1.71 | 1.8 | 1.89 | V |
VCCIO | I/O buffers power supply for LVDS I/O (except for 1SG040HF35 and 1SX040HF35 banks 3C and 3D) | 1.8 V | 1.71 | 1.8 | 1.89 | V |
1.5 V | 1.425 | 1.5 | 1.575 | V | ||
1.35 V | 1.283 | 1.35 | 1.45 | V | ||
1.25 V | 1.19 | 1.25 | 1.31 | V | ||
1.2 V | 1.14 | 1.2 | 1.26 | V | ||
VCCIO3V | I/O buffers power supply for 3 V I/O | 3.0 V | 2.85 | 3 | 3.15 | V |
2.5 V | 2.375 | 2.5 | 2.625 | V | ||
1.8 V | 1.71 | 1.8 | 1.89 | V | ||
1.5 V | 1.425 | 1.5 | 1.575 | V | ||
1.2 V | 1.14 | 1.2 | 1.26 | V | ||
VCCIO3C | I/O buffers power supply for 1SG040HF35 and 1SX040HF35 devices bank 3C only | 3.3 V | 3.135 | 3.3 | 3.465 | V |
3.0 V | 2.85 | 3 | 3.15 | V | ||
VCCIO3D | I/O buffers power supply for 1SG040HF35 and 1SX040HF35 devices bank 3D only | 1.8 V | 1.71 | 1.8 | 1.89 | V |
VCCIO_UIB | Power supply for the Universal Interface Bus between the core and embedded HBM2 memory | 1.2 V | 1.17 | 1.2 | 1.23 | V |
VCCM_WORD | Power supply for the embedded HBM2 memory | — | 2.4 | 2.5 | 2.6 | V |
VCCA_PLL | PLL analog voltage regulator power supply | — | 1.71 | 1.8 | 1.89 | V |
VI 12 13 | DC input voltage | 3.3 V I/O | –0.3 | — | VCCIO + 0.33 | V |
3 V I/O | –0.3 | — | VCCIO + 0.65 | V | ||
LVDS I/O | –0.3 | — | VCCIO + 0.3 | V | ||
VO | Output voltage | — | 0 | — | VCCIO | V |
TJ | Operating junction temperature for Intel® Stratix® 10 MX, NX, and DX 2100 devices | Extended 14 | 0 | — | 100 15 | °C |
Operating junction temperature for Intel® Stratix® 10 GX 10M device | Commercial | 25 | — | 85 | °C | |
Extended | 25 | — | 100 | °C | ||
Operating junction temperature for all other Intel® Stratix® 10 devices | Extended | 0 | — | 100 | °C | |
Industrial | -20 (–40) 16 | — | 100 | °C | ||
tRAMP 17 18 19 | Power supply ramp time | Standard POR | 200 μs | — | 100 ms | — |
Transceiver Power Supply Operating Conditions
Symbol | Description | Datarate | Minimum | Typical | Maximum | Unit |
---|---|---|---|---|---|---|
VCCT_GXB[L,R] and VCCR_GXB[L,R] | Chip-to-chip 20 | 1.0 Gbps to 26.6 Gbps 21 22 | 1.1 | 1.12 | 1.14 | V |
1.0 Gbps to 17.4 Gbps 21 22 | 1.0 | 1.03 23 | 1.06 | V | ||
Backplane 24 | 1.0 Gbps to 12.5 Gbps 21 | 1.0 | 1.03 25, 23 | 1.06 | V | |
VCCH_GXB[L,R] | Transceiver high voltage power | — | 1.71 26 | 1.8 | 1.89 | V |
Symbol | Description | Datarate | Minimum | Typical | Maximum | Unit |
---|---|---|---|---|---|---|
VCCT_GXB[L,R] and VCCR_GXB[L,R] | Chip-to-chip 20 | 1.0 Gbps to 16.0 Gbps 21 | 1.0 | 1.03 23 | 1.06 | V |
> 16.0 Gbps to 17.4 Gbps 21 22 | 1.1 | 1.12 | 1.14 | V | ||
Backplane 24 | 1.0 Gbps to 12.5 Gbps 21 | 1.0 | 1.03 25, 23 | 1.06 | V | |
VCCH_GXB[L,R] | Transceiver high voltage power | — | 1.71 26 | 1.8 | 1.89 | V |
Symbol | Description | Datarate | Minimum | Typical | Maximum | Unit |
---|---|---|---|---|---|---|
VCCT_GXB[L,R] and VCCR_GXB[L,R] | Chip-to-chip 20and Backplane 24 | 1.0 Gbps to 28.3 Gbps (GXT) 21 | 1.1 | 1.12 | 1.14 | V |
1.0 Gbps to 17.4 Gbps (GX) 21 | 1.0 | 1.03 23 | 1.06 | V | ||
VCCH_GXB[L,R] | Transceiver high voltage power | — | 1.71 26 | 1.8 | 1.89 | V |
Symbol | Description | Datarate | Minimum | Typical | Maximum | Unit |
---|---|---|---|---|---|---|
VCCT_GXB[L,R] and VCCR_GXB[L,R] | Chip-to-chip 20 and Backplane 24 | 1.0 Gbps to 16.0 Gbps 21 | 1.0 | 1.03 23 | 1.06 | V |
> 16.0 Gbps to 17.4 Gbps 21 | 1.1 | 1.12 | 1.14 | V | ||
VCCH_GXB[L,R] | Transceiver high voltage power | — | 1.71 26 | 1.8 | 1.89 | V |
Symbol | Description | Minimum 27 | Typical | Maximum 27 | Unit | Noise Mask (at ball grid array (BGA)) |
---|---|---|---|---|---|---|
VCCRT_GXE 28 | Transceiver power supply | 0.87 | 0.9 | 0.93 | V |
20 mVpp (100 kHz to 400 kHz) 3 mVpp (3 MHz to 500 MHz) 10 mVpp at 1 GHz |
VCCRTPLL_GXE 28 | Transceiver PLL power supply | 0.87 | 0.9 | 0.93 | V |
6 mVpp at 100 kHz 1 mVpp (600 kHz to 10 MHz) 10 mVpp at 1 GHz |
VCCH_GXE | Analog power supply | 1.067 | 1.1 | 1.133 | V | 10 mVpp (800 kHz to 500 MHz |
VCCCLK_GXE | LVPECL REFCLK power supply | 2.375 | 2.5 | 2.625 | V | — |
Symbol | Description | Data Rate | Minimum | Typical | Maximum | Unit |
---|---|---|---|---|---|---|
VCCRT_GXP 29 | Transceiver power supply | Up to 16 Gbps 30 | 0.87 | 0.90 | 0.93 | V |
VCCFUSE_GXP 29 | P-tile eFuse power supply | 0.87 | 0.90 | 0.93 | V | |
VCCCLK_GXP 31 32 | P-tile I/O buffer power supply | 1.75 | 1.80 | 1.85 | V | |
VCCH_GXP 31 32 | High voltage power for Transceiver | 1.75 | 1.80 | 1.85 | V |
HPS Power Supply Operating Conditions
Symbol | Description | Condition | Minimum | Typical | Maximum | Unit |
---|---|---|---|---|---|---|
VCCL_HPS | HPS core voltage and periphery circuitry power supply | –E2L, –I2L, –E3X, –I3X | 0.87 | 0.9 | 0.93 | V |
0.91 | 0.94 | 0.97 | V | |||
–E1V, –I1V, –E2V, –I2V, –E3V, –I3V 33 | 0.77 – 0.91 | 0.8 – 0.94 | 0.83 – 0.97 | V | ||
0.87 | 0.9 | 0.93 | V | |||
0.91 | 0.94 | 0.97 | V | |||
VCCPLLDIG_HPS | HPS PLL digital power supply | –E2L, –I2L, –E3X, –I3X | 0.87 | 0.9 | 0.93 | V |
0.91 | 0.94 | 0.97 | V | |||
–E1V, –I1V, –E2V, –I2V, –E3V, –I3V 33 | 0.77 – 0.91 | 0.8 – 0.94 | 0.83 – 0.97 | V | ||
0.87 | 0.9 | 0.93 | V | |||
0.91 | 0.94 | 0.97 | V | |||
VCCPLL_HPS | HPS PLL analog power supply | 1.8 V | 1.71 | 1.8 | 1.89 | V |
VCCIO_HPS | HPS I/O buffers power supply | 1.8 V | 1.71 | 1.8 | 1.89 | V |
DC Characteristics
Supply Current and Power Consumption
Intel offers two ways to estimate power for your design—the Intel® FPGA Power and Thermal Calculator (PTC) and the Intel® Quartus® Prime Power Analyzer feature.
Use the PTC before you start your design to estimate the supply current for your design. The PTC provides a magnitude estimate of the device power because these currents vary greatly with the usage of the resources.
The Intel® Quartus® Prime Power Analyzer provides better quality estimates based on the specifics of the design after you complete place-and-route. The Power Analyzer can apply a combination of user-entered, simulation-derived, and estimated signal activities that, when combined with detailed circuit models, yield very accurate power estimates.
I/O Pin Leakage Current
Symbol | Description | Condition | Min | Max | Unit |
---|---|---|---|---|---|
II | Input pin leakage | VI = 0 V to VCCIOMAX | –80 | 80 | µA |
II_3.3VIO | Input pin leakage for 3.3 V I/O pin | VI = 0 V to VCCIOMAX | –2 | 2 | µA |
IOZ | Tri-stated I/O pin leakage | VO = 0 V to VCCIOMAX | –80 | 80 | µA |
Bus Hold Specifications
The bus-hold trip points are based on calculated input voltages from the JEDEC* standard.
Parameter | Symbol | Condition | VCCIO (V) | Unit | |||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|
1.2 | 1.5 | 1.8 | 2.5 | 3.0 | |||||||||
Min | Max | Min | Max | Min | Max | Min | Max | Min | Max | ||||
Bus-hold, low, sustaining current | ISUSL | VIN > VIL (max) | 8 | — | 12 | — | 30 | — | 60 | — | 70 | — | µA |
Bus-hold, high, sustaining current | ISUSH | VIN < VIH (min) | –8 | — | –12 | — | –30 | — | –60 | — | –70 | — | µA |
Bus-hold, low, overdrive current | IODL | 0 V < VIN < VCCIO | — | 125 | — | 175 | — | 200 | — | 300 | — | 500 | µA |
Bus-hold, high, overdrive current | IODH | 0 V < VIN < VCCIO | — | –125 | — | –175 | — | –200 | — | –300 | — | –500 | µA |
Bus-hold trip point | VTRIP | — | 0.3 | 0.9 | 0.38 | 1.13 | 0.68 | 1.07 | 0.7 | 1.7 | 0.8 | 2 | V |
OCT Calibration Accuracy Specifications
If you enable on-chip termination (OCT) calibration, calibration is automatically performed at power up for I/Os connected to the calibration block.
Symbol | Description | Condition (V) | Calibration Accuracy | Unit | ||
---|---|---|---|---|---|---|
–E1, –I1 | –E2, –I2 | –E3, –I3 | ||||
34-Ω, 48-Ω, 60-Ω, 80-Ω, 120-Ω, and 240-Ω RS | Internal series termination with calibration (34-Ω, 48-Ω, 60-Ω, 80-Ω, 120-Ω, and 240-Ω setting) | VCCIO = 1.2 | ±15 | ±15 | ±15 | % |
34-Ω and 40-Ω RS | Internal series termination with calibration (34-Ω and 40-Ω setting) | VCCIO = 1.5, 1.35, 1.25, 1.2 | ±15 | ±15 | ±15 | % |
25-Ω and 50-Ω RS | Internal series termination with calibration (25-Ω and 50-Ω setting) | VCCIO = 1.8, 1.5, 1.2 | ±15 | ±15 | ±15 | % |
34-Ω, 40-Ω, 48-Ω, 60-Ω, 80-Ω, 120-Ω, and 240-Ω RT | Internal parallel termination with calibration (34-Ω, 40-Ω, 48-Ω, 60-Ω, 80-Ω, 120-Ω, and 240-Ω setting) | POD12 I/O standard,
VCCIO = 1.2 |
±15 | ±15 | ±15 | % |
48-Ω, 50-Ω, 60-Ω, and 120-Ω RT | Internal parallel termination with calibration (48-Ω, 50-Ω, 60-Ω, and 120-Ω setting) | VCCIO = 1.5, 1.2 | –10 to +60 | –10 to +60 | –10 to +60 | % |
48-Ω, 60-Ω, and 120-Ω RT | Internal parallel termination with calibration (48-Ω, 60-Ω, and 120-Ω setting) | VCCIO = 1.25 | –10 to +70 | –10 to +70 | –10 to +70 | % |
48-Ω, 60-Ω, and 120-Ω RT | Internal parallel termination with calibration (48-Ω, 60-Ω, and 120-Ω setting) | VCCIO = 1.35 | –10 to +65 | –10 to +65 | –10 to +65 | % |
50-Ω RT | Internal parallel termination with calibration (50-Ω setting) | VCCIO = 1.8 | –10 to +50 | –10 to +50 | –10 to +50 | % |
OCT Without Calibration Resistance Tolerance Specifications
Symbol | Description | I/O Buffer Type | Condition (V) | Resistance Tolerance | Unit | ||
---|---|---|---|---|---|---|---|
–E1, –I1 | –E2, –I2 | –E3, –I3 | |||||
25-Ω and 50-Ω RS | Internal series termination without calibration (25-Ω and 50-Ω setting) | 3 V I/O | VCCIO = 3.0, 2.5, 1.8, 1.5, 1.2 | –40 to +30 | ±40 | ±40 | % |
25-Ω and 50-Ω RS | Internal series termination without calibration (25-Ω and 50-Ω setting) | LVDS I/O | VCCIO = 1.8, 1.5, 1.2 | –20 to +35 | –20 to +35 | –20 to +35 | % |
34-Ω and 40-Ω RS | Internal series termination without calibration (34-Ω and 40-Ω setting) | LVDS I/O | VCCIO = 1.5, 1.35, 1.25, 1.2 | –20 to +35 | –20 to +35 | –20 to +35 | % |
48-Ω, 60-Ω, 80-Ω, and 240-Ω RS | Internal series termination without calibration (48-Ω, 60-Ω, 80-Ω, and 240-Ω setting) | LVDS I/O | VCCIO = 1.2 | –20 to +35 | –20 to +35 | –20 to +35 | % |
100-Ω RD | Internal differential termination (100-Ω setting) | LVDS I/O | VCCIO = 1.8 | ±25 | ±35 | ±40 | % |
Pin Capacitance
Symbol | Description | Maximum | Unit |
---|---|---|---|
CIO_COLUMN | Input capacitance on column I/O pins | 3.5 | pF |
CIO_3.3VIO | Input/output capacitance of I/O pins | 5 | pF |
COUTFB | Input capacitance on dual-purpose clock output/feedback pins | 3.5 | pF |
Internal Weak Pull-Up Resistor
All I/O pins, except configuration, test, and JTAG pins, have an option to enable weak pull-up. For SDM and HPS, the configuration I/O and peripheral I/O are supported with weak pull-up and weak pull-down options. The internal weak pull-down feature is only supported in selected HPS and SDM I/O. The typical value for this internal weak pull-down resistor is approximately 25 kΩ.
Symbol | Description | Condition (V) | Nominal Value | Resistance Tolerance | Unit |
---|---|---|---|---|---|
RPU | Value of the I/O pin pull-up resistor before and during configuration, as well as user mode if you have enabled the programmable pull-up resistor option. | VCCIO = 3.0 ±5% | 25 | ±25% | kΩ |
VCCIO = 2.5 ±5% | 25 | ±25% | kΩ | ||
VCCIO = 1.8 ±5% | 25 | ±25% | kΩ | ||
VCCIO = 1.5 ±5% | 25 | ±25% | kΩ | ||
VCCIO = 1.35 ±5% | 25 | ±25% | kΩ | ||
VCCIO = 1.25 ±5% | 25 | ±25% | kΩ | ||
VCCIO = 1.2 ±5% | 25 | ±25% | kΩ |
I/O Standard Specifications
Tables in this section list the input voltage (VIH and VIL), output voltage (VOH and VOL), and current drive characteristics (IOH and IOL) for various I/O standards supported by Intel® Stratix® 10 devices.
For minimum voltage values, use the minimum VCCIO values. For maximum voltage values, use the maximum VCCIO values.
You must perform timing closure analysis to determine the maximum achievable frequency for general purpose I/O standards.
Single-Ended I/O Standards Specifications
I/O Standard | VCCIO (V) | VIL(V) | VIH(V) | VOL (V) | VOH (V) | IOL 34 (mA) | IOH 34 (mA) | ||||
---|---|---|---|---|---|---|---|---|---|---|---|
Min | Typ | Max | Min | Max | Min | Max | Max | Min | |||
3.3 V LVTTL, 3.3 V LVCMOS 35 | 3.135 | 3.3 | 3.465 | –0.3 | 0.8 | 2 | 3.6 | 0.4 | 2.4 | 4 | –4 |
3.0 V LVTTL, 3.0 V LVCMOS 35 | 2.85 | 3 | 3.15 | –0.3 | 0.8 | 2 | 3.6 | 0.4 | 2.4 | 4 | –4 |
3.0 V LVTTL | 2.85 | 3 | 3.15 | –0.3 | 0.8 | 1.7 | 3.6 | 0.4 | 2.4 | 2 | –2 |
3.0 V LVCMOS | 2.85 | 3 | 3.15 | –0.3 | 0.8 | 1.7 | 3.6 | 0.2 | VCCIO – 0.2 | 0.1 | –0.1 |
2.5 V | 2.375 | 2.5 | 2.625 | –0.3 | 0.7 | 1.7 | 3.3 | 0.4 | 2 | 1 | –1 |
1.8 V | 1.71 | 1.8 | 1.89 | -0.3 | 0.35 × VCCIO | 0.65 × VCCIO | VCCIO + 0.3 | 0.45 | VCCIO – 0.45 | 2 | –2 |
1.5 V | 1.425 | 1.5 | 1.575 | –0.3 | 0.35 × VCCIO | 0.65 × VCCIO | VCCIO + 0.3 | 0.25 × VCCIO | 0.75 × VCCIO | 2 | –2 |
1.2 V | 1.14 | 1.2 | 1.26 | –0.3 | 0.35 × VCCIO | 0.65 × VCCIO | VCCIO + 0.3 | 0.25 × VCCIO | 0.75 × VCCIO | 2 | –2 |
Schmitt Trigger Input | 1.71 | 1.8 | 1.89 | — | 0.35 × VCCIO | 0.65 × VCCIO | — | — | — | — | — |
Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications
I/O Standard | VCCIO (V) | VREF (V) | VTT (V) | ||||||
---|---|---|---|---|---|---|---|---|---|
Min | Typ | Max | Min | Typ | Max | Min | Typ | Max | |
SSTL-18 Class I, II | 1.71 | 1.8 | 1.89 | 0.833 | 0.9 | 0.969 | VREF - 0.04 | VREF | VREF + 0.04 |
SSTL-15 Class I, II | 1.425 | 1.5 | 1.575 | 0.49 × VCCIO | 0.5 × VCCIO | 0.51 × VCCIO | 0.49 × VCCIO | 0.5 × VCCIO | 0.51 × VCCIO |
SSTL-135 | 1.283 | 1.35 | 1.45 | 0.49 × VCCIO | 0.5 × VCCIO | 0.51 × VCCIO | 0.49 × VCCIO | 0.5 × VCCIO | 0.51 × VCCIO |
SSTL-125 | 1.19 | 1.25 | 1.31 | 0.49 × VCCIO | 0.5 × VCCIO | 0.51 × VCCIO | 0.49 × VCCIO | 0.5 × VCCIO | 0.51 × VCCIO |
SSTL-12 | 1.14 | 1.2 | 1.26 | 0.49 × VCCIO | 0.5 × VCCIO | 0.51 × VCCIO | 0.49 × VCCIO | 0.5 × VCCIO | 0.51 × VCCIO |
HSTL-18 Class I, II | 1.71 | 1.8 | 1.89 | 0.85 | 0.9 | 0.95 | — | VCCIO/2 | — |
HSTL-15 Class I, II | 1.425 | 1.5 | 1.575 | 0.68 | 0.75 | 0.9 | — | VCCIO/2 | — |
HSTL-12 Class I, II | 1.14 | 1.2 | 1.26 | 0.47 × VCCIO | 0.5 × VCCIO | 0.53 × VCCIO | — | VCCIO/2 | — |
HSUL-12 | 1.14 | 1.2 | 1.3 | 0.49 × VCCIO | 0.5 × VCCIO | 0.51 × VCCIO | — | — | — |
POD12 | 1.14 | 1.2 | 1.26 | — | Internally calibrated | — | — | VCCIO | — |
Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications
I/O Standard | VIL(DC) (V) | VIH(DC) (V) | VIL(AC) (V) | VIH(AC) (V) | VOL (V) | VOH (V) | IOL 36 (mA) | IOH 36 (mA) | ||
---|---|---|---|---|---|---|---|---|---|---|
Min | Max | Min | Max | Max | Min | Max | Min | |||
SSTL-18 Class I | –0.3 | VREF –0.125 | VREF + 0.125 | VCCIO + 0.3 | VREF – 0.25 | VREF + 0.25 | VTT – 0.603 | VTT + 0.603 | 6.7 | –6.7 |
SSTL-18 Class II | –0.3 | VREF –0.125 | VREF + 0.125 | VCCIO + 0.3 | VREF – 0.25 | VREF + 0.25 | 0.28 | VCCIO –0.28 | 13.4 | –13.4 |
SSTL-15 Class I | — | VREF – 0.1 | VREF + 0.1 | — | VREF – 0.175 | VREF + 0.175 | 0.2 × VCCIO | 0.8 × VCCIO | 8 | –8 |
SSTL-15 Class II | — | VREF – 0.1 | VREF + 0.1 | — | VREF – 0.175 | VREF + 0.175 | 0.2 × VCCIO | 0.8 × VCCIO | 16 | –16 |
SSTL-135 | — | VREF – 0.09 | VREF + 0.09 | — | VREF – 0.16 | VREF + 0.16 | 0.2 × VCCIO | 0.8 × VCCIO | — | — |
SSTL-125 | — | VREF – 0.09 | VREF + 0.09 | — | VREF – 0.15 | VREF + 0.15 | 0.2 × VCCIO | 0.8 × VCCIO | — | — |
SSTL-12 | — | VREF – 0.10 | VREF + 0.10 | — | VREF – 0.15 | VREF + 0.15 | 0.2 × VCCIO | 0.8 × VCCIO | — | — |
HSTL-18 Class I | — | VREF –0.1 | VREF + 0.1 | — | VREF – 0.2 | VREF + 0.2 | 0.4 | VCCIO – 0.4 | 8 | –8 |
HSTL-18 Class II | — | VREF – 0.1 | VREF + 0.1 | — | VREF – 0.2 | VREF + 0.2 | 0.4 | VCCIO – 0.4 | 16 | –16 |
HSTL-15 Class I | — | VREF – 0.1 | VREF + 0.1 | — | VREF – 0.2 | VREF + 0.2 | 0.4 | VCCIO – 0.4 | 8 | –8 |
HSTL-15 Class II | — | VREF – 0.1 | VREF + 0.1 | — | VREF – 0.2 | VREF + 0.2 | 0.4 | VCCIO –0.4 | 16 | –16 |
HSTL-12 Class I | –0.15 | VREF – 0.08 | VREF + 0.08 | VCCIO + 0.15 | VREF – 0.15 | VREF + 0.15 | 0.25 × VCCIO | 0.75 × VCCIO | 8 | –8 |
HSTL-12 Class II | –0.15 | VREF – 0.08 | VREF + 0.08 | VCCIO + 0.15 | VREF – 0.15 | VREF + 0.15 | 0.25 × VCCIO | 0.75 × VCCIO | 16 | –16 |
HSUL-12 | — | VREF – 0.13 | VREF + 0.13 | — | VREF – 0.22 | VREF + 0.22 | 0.1 × VCCIO | 0.9 × VCCIO | — | — |
POD12 | –0.15 | VREF – 0.08 | VREF + 0.08 | VCCIO + 0.15 | VREF – 0.15 | VREF + 0.15 | — | — | — | — |
Differential SSTL I/O Standards Specifications
I/O Standard | VCCIO (V) | VSWING(DC) (V) | VSWING(AC) (V) | VIX(AC) (V) | ||||||
---|---|---|---|---|---|---|---|---|---|---|
Min | Typ | Max | Min | Max | Min | Max | Min | Typ | Max | |
SSTL-18 Class I, II | 1.71 | 1.8 | 1.89 | 0.25 | VCCIO + 0.6 | 0.5 | VCCIO + 0.6 | VCCIO/2 – 0.175 | — | VCCIO/2 + 0.175 |
SSTL-15 Class I, II | 1.425 | 1.5 | 1.575 | 0.2 | 37 | 2(VIH(AC) – VREF) | 2(VREF – VIL(AC)) | VCCIO/2 – 0.15 | — | VCCIO/2 + 0.15 |
SSTL-135 | 1.283 | 1.35 | 1.45 | 0.18 | 37 | 2(VIH(AC) – VREF) | 2(VIL(AC) – VREF) | VCCIO/2 – 0.15 | — | VCCIO/2 + 0.15 |
SSTL-125 | 1.19 | 1.25 | 1.31 | 0.18 | 37 | 2(VIH(AC) – VREF) | 2(VIL(AC) – VREF) | VCCIO/2 – 0.15 | — | VCCIO/2 + 0.15 |
SSTL-12 | 1.14 | 1.2 | 1.26 | 0.16 | 37 | 2(VIH(AC) – VREF) | 2(VIL(AC) – VREF) | VREF – 0.15 | VCCIO/2 | VREF + 0.15 |
Differential HSTL and HSUL I/O Standards Specifications
I/O Standard | VCCIO (V) | VDIF(DC) (V) | VDIF(AC) (V) | VX(AC) (V) | VCM(DC) (V) | ||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Min | Typ | Max | Min | Max | Min | Max | Min | Typ | Max | Min | Typ | Max | |
HSTL-18 Class I, II | 1.71 | 1.8 | 1.89 | 0.2 | — | 0.4 | — | 0.78 | — | 1.12 | 0.78 | — | 1.12 |
HSTL-15 Class I, II | 1.425 | 1.5 | 1.575 | 0.2 | — | 0.4 | — | 0.68 | — | 0.9 | 0.68 | — | 0.9 |
HSTL-12 Class I, II | 1.14 | 1.2 | 1.26 | 0.16 | VCCIO + 0.3 | 0.3 | VCCIO + 0.48 | — | 0.5 × VCCIO | — | 0.4 × VCCIO | 0.5 × VCCIO | 0.6 × VCCIO |
HSUL-12 | 1.14 | 1.2 | 1.3 | 2(VIH(DC) – VREF) | 2(VREF – VIH(DC)) | 2(VIH(AC) – VREF) | 2(VREF – VIH(AC)) | 0.5 × VCCIO – 0.12 | 0.5 × VCCIO | 0.5 × VCCIO +0.12 | 0.4 × VCCIO | 0.5 × VCCIO | 0.6 × VCCIO |
Differential I/O Standards Specifications
I/O Standard | VCCIO (V) | VID (mV) 38 | VICM(DC) (V) | VOD (V) 39 40 | VOCM (V) 39 | |||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Min | Typ | Max | Min | Max | Min | Condition | Max | Min | Typ | Max | Min | Typ | Max | |
LVDS 41 | 1.71 | 1.8 | 1.89 | 100 | — | 0.05 | Data rate ≤700 Mbps | 1.65 | 0.247 | — | 0.6 | 1.125 | 1.25 | 1.375 |
1 | Data rate >700 Mbps | 1.6 | ||||||||||||
RSDS 42 | 1.71 | 1.8 | 1.89 | 100 | — | 0.3 | — | 1.4 | 0.1 | 0.2 | 0.6 | 0.5 | 1.2 | 1.4 |
Mini-LVDS 43 | 1.71 | 1.8 | 1.89 | 200 | 600 | 0.4 | — | 1.325 | 0.25 | — | 0.6 | 1 | 1.2 | 1.4 |
LVPECL 44 | 1.71 | 1.8 | 1.89 | 300 | — | 0.6 | Data rate ≤700 Mbps | 1.7 | — | — | — | — | — | — |
1 | Data rate >700 Mbps | 1.6 |
Switching Characteristics
This section provides the performance characteristics of Intel® Stratix® 10 core and periphery blocks.
Core Performance Specifications
Clock Tree Specifications
Parameter | Performance | Unit | ||
---|---|---|---|---|
–E1V, –I1V | –E2V, –E2L, –I2V, –I2L, –C2L | –E3V, –E3X, –I3V, –I3X | ||
Programmable clock routing | 1,000 | 900 | 780 | MHz |
PLL Specifications
Fractional PLL Specifications
Symbol | Parameter | Condition | Min | Typ | Max | Unit |
---|---|---|---|---|---|---|
fIN | Input clock frequency | — | 29 | — | 800 45 | MHz |
fINPFD | Input clock frequency to the phase frequency detector (PFD) | — | 29 | — | 700 | MHz |
fVCO | PLL voltage-controlled oscillator (VCO) operating range for core applications | — | 6 | — | 14.025 | GHz |
tEINDUTY | Input clock duty cycle | — | 40 | — | 60 | % |
fOUT | Output frequency for internal clock | — | — | — | 1 | GHz |
fDYCONFIGCLK | Dynamic configuration clock for reconfig_clk | — | — | — | 125 | MHz |
tLOCK | Time required to lock from end-of-device configuration | — | — | — | 1 | ms |
tDLOCK | Time required to lock dynamically (after switchover or reconfiguring any non-post-scale counters/delays) | — | — | — | 1 | ms |
fCLBW | PLL closed-loop bandwidth | — | 0.3 | — | 4 | MHz |
tINCCJ 46, 47 | Input clock cycle-to-cycle jitter | FREF ≥ 100 MHz | — | — | 0.13 | UI (p-p) |
FREF < 100 MHz | — | — | ±650 | ps (p-p) | ||
tOUTPJ 48 | Period jitter for clock output | FOUT ≥ 100 MHz | — | — | 600 | ps (p-p) |
FOUT < 100 MHz | — | — | 60 | mUI (p-p) | ||
tOUTCCJ 48 | Cycle-to-cycle jitter for clock output | FOUT ≥ 100 MHz | — | — | 600 | ps (p-p) |
FOUT < 100 MHz | — | — | 60 | mUI (p-p) | ||
dKBIT | Bit number of Delta Sigma Modulator (DSM) | — | — | 32 | — | bit |
I/O PLL Specifications
Symbol | Parameter | Condition | Min | Typ | Max | Unit |
---|---|---|---|---|---|---|
fIN | Input clock frequency | –1 speed grade | 10 | — | 1,100 49 | MHz |
–2 speed grade | 10 | — | 900 49 | MHz | ||
–3 speed grade | 10 | — | 750 49 | MHz | ||
fINPFD | Input clock frequency to the PFD | — | 10 | — | 325 | MHz |
fVCO | PLL VCO operating range | –1 speed grade | 600 | — | 1,600 | MHz |
–2 speed grade | 600 | — | 1,434 | MHz | ||
–3 speed grade | 600 | — | 1,280 50 | MHz | ||
fCLBW | PLL closed-loop bandwidth | — | 0.5 | — | 10 | MHz |
tEINDUTY | Input clock or external feedback clock input duty cycle | — | 40 | — | 60 | % |
fOUT | Output frequency for internal clock (C counter) | –1 speed grade | — | — | 1,100 | MHz |
–2 speed grade | — | — | 900 | MHz | ||
–3 speed grade | — | — | 750 | MHz | ||
fOUT_EXT | Output frequency for external clock output | –1 speed grade | — | — | 800 | MHz |
–2 speed grade | — | — | 720 | MHz | ||
–3 speed grade | — | — | 650 | MHz | ||
tOUTDUTY | Duty cycle for dedicated external clock output (when set to 50%) | — | 45 | 50 | 55 | % |
tFCOMP | External feedback clock compensation time | — | — | — | 5 | ns |
fDYCONFIGCLK | Dynamic configuration clock for mgmt_clk and scanclk | — | — | — | 200 | MHz |
tLOCK | Time required to lock from end-of-device configuration or deassertion of areset | — | — | — | 1 | ms |
tDLOCK | Time required to lock dynamically (after switchover or reconfiguring any non-post-scale counters/delays) | — | — | — | 1 | ms |
tPLL_PSERR | Accuracy of PLL phase shift | — | — | — | ±50 | ps |
tARESET | Minimum pulse width on the areset signal | — | 10 | — | — | ns |
tINCCJ 51 52 | Input clock cycle-to-cycle jitter | FREF ≥ 100 MHz | — | — | 0.15 | UI (p-p) |
FREF < 100 MHz | — | — | ±750 | ps (p-p) | ||
tOUTPJ_DC | Period jitter for dedicated clock output | FOUT ≥ 100 MHz | — | — | 175 | ps (p-p) |
FOUT < 100 MHz | — | — | 17.5 | mUI (p-p) | ||
tOUTCCJ_DC | Cycle-to-cycle jitter for dedicated clock output | FOUT ≥ 100 MHz | — | — | 175 | ps (p-p) |
FOUT < 100 MHz | — | — | 17.5 | mUI (p-p) | ||
tOUTPJ_IO 53 | Period jitter for clock output on the regular I/O | FOUT ≥ 100 MHz | — | — | 600 | ps (p-p) |
FOUT < 100 MHz | — | — | 60 | mUI (p-p) | ||
tOUTCCJ_IO 53 | Cycle-to-cycle jitter for clock output on the regular I/O | FOUT ≥ 100 MHz | — | — | 600 | ps (p-p) |
FOUT < 100 MHz | — | — | 60 | mUI (p-p) | ||
tCASC_OUTPJ_DC | Period jitter for dedicated clock output in cascaded PLLs through dedicated cascade path and core clock fabric | FOUT ≥ 100 MHz | — | — | 175 | ps (p-p) |
FOUT < 100 MHz | — | — | 17.5 | mUI (p-p) |
DSP Block Specifications
Mode | Performance | Unit | ||
---|---|---|---|---|
–E1V, –I1V | –E2V, –E2L, –I2V, –I2L, –C2L | –E3V, –E3X, –I3V, –I3X | ||
Fixed-point 18 × 19 multiplication mode | 1,000 | 771 | 667 | MHz |
Fixed-point 27 × 27 multiplication mode 54 | 1,000 | 771 | 667 | MHz |
Fixed-point 18 × 18 multiplier adder mode 54 | 1,000 | 771 | 667 | MHz |
Fixed-point 18 × 18 multiplier adder summed with 36-bit input mode 54 | 1,000 | 771 | 667 | MHz |
Fixed-point 18 × 19 systolic mode | 1,000 | 771 | 667 | MHz |
Complex 18 × 19 multiplication mode | 1,000 | 771 | 667 | MHz |
Floating point multiplication mode | 750 | 579 | 500 | MHz |
Floating point adder or subtract mode | 750 | 579 | 500 | MHz |
Floating point multiplier adder or subtract mode | 750 | 579 | 500 | MHz |
Floating point multiplier accumulate mode | 750 | 579 | 500 | MHz |
Floating point vector one mode | 750 | 579 | 500 | MHz |
Floating point vector two mode | 750 | 579 | 500 | MHz |
- –E1V and –I1V: 750 MHz
- –E2V, –E2L, –I2V, –I2L, and –C2L: 578 MHz
- –E3V, –E3X, –I3V, and –I3X: 507 MHz
Memory Block Specifications
To achieve the maximum memory block performance, use a memory block clock that comes through global clock routing from an on-chip PLL and set to 50% output duty cycle. Use the Intel® Quartus® Prime software to report timing for the memory block clocking schemes.
When you use the error detection cyclical redundancy check (CRC) feature, there is no degradation in fMAX.
Memory | Mode | Performance | |||
---|---|---|---|---|---|
–E1V, –I1V | –E2V, –E2L, –I2V, –I2L, –C2L | –E3V, –E3X, –I3V, –I3X | Unit | ||
MLAB | Single port, all supported widths (×16/×32) | 1,000 | 782 | 667 | MHz |
Simple dual-port, all supported widths (×16/×32) | 1,000 | 782 | 667 | MHz | |
Simple dual-port with read-during-write option | 550 | 450 | 400 | MHz | |
ROM, all supported width (×16/×32) | 1,000 | 782 | 667 | MHz | |
M20K Block | Single-port, all supported widths | 1,000 | 782 | 667 | MHz |
Simple dual-port, all supported widths | 1,000 | 782 | 667 | MHz | |
Simple dual-port, coherent read enabled | 1,000 | 782 | 667 | MHz | |
Simple dual-port with the read-during-write option set to Old Data, all supported widths | 800 | 640 | 560 | MHz | |
Simple dual-port with ECC enabled, 512 × 32 | 600 | 480 | 420 | MHz | |
Simple dual-port with ECC, optional pipeline registers enabled, and fast write mode, 512 × 32 | 1,000 | 782 | 667 | MHz | |
Simple dual-port with ECC and optional pipeline registers enabled, with the read-during-write option set to Old Data, 512 × 32 | 1,000 | 750 | 667 | MHz | |
True dual port, all supported widths | 600 | 500 | 420 | MHz | |
Simple quad-port, all supported widths | 600 | 480 | 420 | MHz | |
ROM (single port), all supported widths | 1,000 | 782 | 667 | MHz | |
ROM (dual port), all supported widths | 600 | 500 | 420 | MHz | |
eSRAM 55 56 | Simple dual-port | 200–750 | 200–640 | 200–500 | MHz |
- 466.51 MHz – 499.99 MHz
- 233.26 MHz – 249.99 MHz
Direct Interface Bus (DIB) Specifications
Mode | Maximum DIB Clock (MHz) | DIB-DIB Latency (ns) |
---|---|---|
BYPASS mode (1:1) | — | 2.5 |
ASYNC mode (1:1, 2:1, 4:1 TDM) | 400 | — |
SYNC mode (1:1, 2:1, 4:1 TDM) | 400 | — |
Internal Temperature Sensing Diode Specifications
External Temperature Sensing Diode Specifications
Description | Min | Typ | Max | Unit |
---|---|---|---|---|
Ibias, diode source current (core fabric, L-Tile, H-Tile, E-Tile, and P-Tile TSD) | 10 | — | 170 | μA |
Vbias, voltage across diode (core fabric, L-Tile, and H-Tile TSD) | 0.35 | — | 0.9 | V |
Vbias, voltage across diode (E-Tile TSD) | 0.56 | — | 0.82 | V |
Vbias, voltage across diode (P-Tile TSD) | 0.56 | — | 0.87 | V |
Series resistance (core fabric TSD) | — | — | < 11 | Ω |
Series resistance (L-Tile and H-Tile TSD) | — | — | < 17 | Ω |
Series resistance (E-Tile TSD) | — | — | < 2 | Ω |
Series resistance (P-Tile TSD) | — | — | < 10 | Ω |
Diode ideality factor (core fabric TSD) | — | 1.006 | — | — |
Diode ideality factor (L-Tile and H-Tile TSD) 58 | — | 1.003 | — | — |
Diode ideality factor (E-Tile TSD) | — | 1.005 | — | — |
Diode ideality factor (P-Tile TSD) 58 | — | 1.0108 | — | — |
Internal Voltage Sensor Specifications
Parameter | Minimum | Typical | Maximum | Unit | |
---|---|---|---|---|---|
Resolution | — | 8 | — | Bit | |
Sampling rate | — | — | 1.0 | KSPS | |
Differential non-linearity (DNL) | — | — | ±1 | LSB | |
Integral non-linearity (INL) | — | — | ±1 | LSB | |
Input capacitance | — | — | 40 | pF | |
Voltage sensor accuracy, Vin range: 0 V to 1.24 V | –3 | — | 3 | % | |
Unipolar Input Mode | Input signal range for Vsigp | 0 | — | 1.49 | V |
Common mode voltage on Vsign | 0 | — | 0.25 | V | |
Input signal range for Vsigp – Vsign | 0 | — | 1.24 | V |
Periphery Performance Specifications
This section describes the periphery performance, high-speed I/O, and external memory interface.
Actual achievable frequency depends on design and system specific factors. Ensure proper timing closure in your design and perform HSPICE/IBIS simulations based on your specific design and system setup to determine the maximum achievable frequency in your system.
High-Speed I/O Specifications
Symbol | Condition | –E1V, –I1V | –E2V, –E2L, –I2L, –I2V, –C2L | –E3V, –E3X, –I3X, –I3V | Unit | |||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|
Min | Typ | Max | Min | Typ | Max | Min | Typ | Max | ||||
fHSCLK_in (input clock frequency) True Differential I/O Standards | Clock boost factor W = 1 to 40 59 | 10 | — | 800 | 10 | — | 700 | 10 | — | 625 | MHz | |
fHSCLK_in (input clock frequency) Single-Ended I/O Standards | Clock boost factor W = 1 to 40 59 | 10 | — | 625 | 10 | — | 625 | 10 | — | 525 | MHz | |
fHSCLK_OUT (output clock frequency) | — | — | — | 800 60 | — | — | 700 60 | — | — | 625 60 | MHz | |
Transmitter | True Differential I/O Standards - fHSDR (data rate) 61 | SERDES factor J = 4 to 10 62 64 63 | 64 | — | 1,600 | 64 | — | 1,434 65 | 64 | — | 1,250 | Mbps |
SERDES factor J = 3 62 64 63 | 64 | — | 1,000 | 64 | — | 1,000 | 64 | — | 938 | Mbps | ||
SERDES factor J = 2, uses DDR registers | 64 | — | 840 66 | 64 | — | 66 | 64 | — | 66 | Mbps | ||
SERDES factor J = 1, uses DDR registers | 64 | — | 420 66 | 64 | — | 66 | 64 | — | 66 | Mbps | ||
tx Jitter - True Differential I/O Standards | Total jitter for data rate, 600 Mbps – 1.6 Gbps | — | — | 160 | — | — | 200 | — | — | 250 | ps | |
Total jitter for data rate, < 600 Mbps | — | — | 0.1 | — | — | 0.12 | — | — | 0.15 | UI | ||
tDUTY 67 | TX output clock duty cycle for Differential I/O Standards | 45 | 50 | 55 | 45 | 50 | 55 | 45 | 50 | 55 | % | |
tRISE & tFALL 63 68 | True Differential I/O Standards | — | — | 160 | — | — | 180 | — | — | 200 | ps | |
TCCS 67 61 | True Differential I/O Standards | — | — | 330 | — | — | 330 | — | — | 330 | ps | |
Receiver | True Differential I/O Standards - fHSDRDPA (data rate) | SERDES factor J = 4 to 10 62 64 63 | 150 | — | 1,600 | 150 | — | 1,43465 | 150 | — | 1,250 | Mbps |
SERDES factor J = 3 62 64 63 | 150 | — | 1,000 | 150 | — | 1,000 | 150 | — | 938 | Mbps | ||
fHSDR (data rate) (without DPA) 61 | SERDES factor J = 3 to 10 | 64 | — | 69 | 64 | — | 69 | 64 | — | 69 | Mbps | |
SERDES factor J = 2, uses DDR registers | 64 | — | 66 | 64 | — | 66 | 64 | — | 66 | Mbps | ||
SERDES factor J = 1, uses DDR registers | 64 | — | 66 | 64 | — | 66 | 64 | — | 66 | Mbps | ||
DPA (FIFO mode) | DPA run length | — | — | — | 10,000 | — | — | 10,000 | — | — | 10,000 | UI |
DPA (soft CDR mode) | DPA run length | SGMII/GbE protocol | — | — | 5 | — | — | 5 | — | — | 5 | UI |
All other protocols | — | — | 50 data transition per 208 UI | — | — | 50 data transition per 208 UI | — | — | 50 data transition per 208 UI | — | ||
Soft CDR mode | Soft-CDR ppm tolerance | — | –300 | — | 300 | –300 | — | 300 | –300 | — | 300 | ppm |
Non DPA mode | Sampling Window | — | — | — | 330 | — | — | 330 | — | — | 330 | ps |
DPA Lock Time Specifications
Standard | Training Pattern | Number of Data Transitions in One Repetition of the Training Pattern | Number of Repetitions per 256 Data Transitions 70 | Maximum Data Transition 71 |
---|---|---|---|---|
SPI-4 | 00000000001111111111 | 2 | 128 | 768 |
Parallel Rapid I/O | 00001111 | 2 | 128 | 768 |
10010000 | 4 | 64 | 768 | |
Miscellaneous | 10101010 | 8 | 32 | 768 |
01010101 | 8 | 32 | 768 |
LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specifications
Jitter Frequency (Hz) | Sinusoidal Jitter (UI) | |
---|---|---|
F1 | 10,000 | 25.00 |
F2 | 17,565 | 25.00 |
F3 | 1,493,000 | 0.28 |
F4 | 50,000,000 | 0.28 |
Memory Standards Supported by the Hard Memory Controller
Memory Standard | Rate Support | Ping Pong PHY Support | Maximum Frequency (MHz) |
---|---|---|---|
DDR4 SDRAM | Quarter rate | Yes | 1,333 |
DDR3 SDRAM | Quarter rate 72 | Yes | 1,066 |
DDR3L SDRAM | Quarter rate | Yes | 1,066 |
Memory Standards Supported by the Soft Memory Controller
Memory Standard | Rate Support | Maximum Frequency (MHz) |
---|---|---|
RLDRAM 3 73 | Quarter rate | 1,200 |
QDR IV SRAM | Quarter rate | 1,066 |
DDR-T | Quarter rate | 1,200 |
QDR II SRAM | Full rate | 333 |
QDR II+ SRAM | Half rate | 550 |
QDR II+ Xtreme SRAM | Half rate | 633 |
Memory Standards Supported by the HPS Hard Memory Controller
Memory Standard | Rate Support | Maximum Frequency (MHz) |
---|---|---|
DDR4 SDRAM | Half rate | 1,066 |
DDR3 SDRAM | Half rate | 1,066 |
DDR3L SDRAM | Half rate | 1,066 |
DLL Range Specifications
Parameter | Performance (for All Speed Grades) | Unit |
---|---|---|
DLL operating frequency range | 600 – 1,333 74 | MHz |
DLL reference clock input | Minimum 600 | MHz |
Memory Output Clock Jitter Specifications
The clock jitter specification applies to the memory output clock pins clocked by an I/O PLL, or generated using differential signal-splitter and double data I/O circuits clocked by a PLL output routed on a PHY clock network as specified. Intel recommends using PHY clock networks for better jitter performance.
The memory clock output jitter is within the JEDEC* specifications with an input of 10 ps peak-to-peak jitter.
Performance Specifications of the HBM2 Interface in Intel Stratix 10 MX, NX, and DX 2100 Devices
Intel® Stratix® 10 Device Speed Grade | Maximum HBM2 Interface Frequency (MHz) |
---|---|
–1 | 1,000 |
–2 | 800 |
–3 | 600 |
HBM2 Interface Performance


OCT Calibration Block Specifications
Symbol | Description | Min | Typ | Max | Unit |
---|---|---|---|---|---|
OCTUSRCLK | Clock required by OCT calibration blocks | — | — | 20 | MHz |
TOCTCAL | Number of OCTUSRCLK clock cycles required for RS OCT /RT OCT calibration | > 2000 | — | — | Cycles |
TOCTSHIFT | Number of OCTUSRCLK clock cycles required for OCT code to shift out | — | 32 | — | Cycles |
TRS_RT | Time required between the dyn_term_ctrl and oe signal transitions in a bidirectional I/O buffer to dynamically switch between RS OCT and RT OCT | — | 8 | — | Full-rate cycle |
L-Tile Transceiver Performance Specifications
Transceiver Performance for Intel Stratix 10 GX/SX L-Tile Devices
Symbol/Description | Transceiver Speed Grade | ||
---|---|---|---|
-1 | -2 | -3 | |
Chip-to-chip | N/A | 26.6 Gbps 8 channels per tile 75 |
17.4 Gbps |
Backplane | N/A | 12.5 Gbps | 12.5 Gbps |
Symbol/Description | Condition | Transceiver Speed Grade 2 | Transceiver Speed Grade 3 | Unit |
---|---|---|---|---|
Supported Output Frequency | Maximum Frequency | 13.3 | 8.7 | GHz |
Minimum Frequency | 500 | MHz | ||
tLOCK 76 | Maximum Frequency | 1 | ms | |
tARESET Required Reset Time 77 78 | — | 25 | Avalon Clock Cycles |
Symbol/Description | Condition | Mode | All Transceiver Speed Grades | Unit |
---|---|---|---|---|
Supported Output Frequency (VCO frequency based) | Maximum datarate | Transceiver - HDMI | 12.5 | Gbps |
Transceiver - General | 12.5 | |||
Transceiver - OTN, SDI Cascade | 14.025 | |||
Minimum datarate | Transceiver - HDMI | 4.6 | Gbps | |
Transceiver - General | 6 | |||
Transceiver - OTN, SDI Cascade | 7 | |||
tLOCK 76 | Maximum Frequency | 1 | ms | |
tARESET Required Reset Time 77 78 | — | 25 | Avalon Clock Cycles |
Transceiver Specifications for Intel Stratix 10 GX/SX L-Tile Devices
Symbol/Description | Condition | All Transceiver Speed Grades | Unit | ||
---|---|---|---|---|---|
Min | Typ | Max | |||
Supported I/O Standards | Dedicated reference clock pin | CML, Differential LVPECL, LVDS, and HCSL | |||
RX reference clock pin | CML, Differential LVPECL, and LVDS | ||||
Input Reference Clock Frequency (CMU PLL) |
50 | — | 800 | MHz | |
Input Reference Clock Frequency (ATX PLL) |
100 | — | 800 | MHz | |
Input Reference Clock Frequency (fPLL) |
50 79 | — | 800 | MHz | |
Rise time | 20% to 80% | — | — | 350 | ps |
Fall time | 80% to 20% | — | — | 350 | ps |
Duty cycle | — | 45 | — | 55 | % |
Spread-spectrum modulating clock frequency | PCIe | 30 | — | 33 | kHz |
Spread-spectrum downspread | PCIe | — | 0 to –0.5 | — | % |
On-chip termination resistors | — | — | 100 | — | Ω |
Absolute VMAX | Dedicated reference clock pin | — | — | 1.6 | V |
RX reference clock pin | — | — | 1.2 | V | |
Absolute VMIN | — | –0.4 | — | — | V |
Peak-to-peak differential input voltage | — | 200 | — | 1600 | mV |
VICM (AC coupled) | VCCR_GXB =1.03 V | — | 0 | — | V |
VICM (DC coupled) | HCSL I/O standard for PCIe reference clock | 250 | — | 550 | mV |
Transmitter REFCLK Phase Noise (800 MHz) 80 | 100 Hz | — | — | –70 | dBc/Hz |
1 kHz | — | — | –90 | dBc/Hz | |
10 kHz | — | — | –100 | dBc/Hz | |
100 kHz | — | — | –110 | dBc/Hz | |
≥ 1 MHz | — | — | –120 | dBc/Hz | |
RREF | — | 2.0 k ±1% | — | 2.0 k ±1% | Ω |
TSSC-MAX-PERIOD-SLEW | Max spread spectrum clocking (SSC) df/dt | 0.75 |
Clock Network | Maximum Performance 81 | Channel Span | Unit | ||
---|---|---|---|---|---|
ATX | fPLL | CMU | |||
x1 | 17.4 | 12.5 | 10.3125 | 6 channels | Gbps |
x6 | 17.4 | 12.5 | N/A | 6 channels | Gbps |
x24 | 17.4 85 | 12.5 | N/A |
2 banks up and 1 bank down (total 24 channels) or 2 banks down and 1 bank up (total 24 channels) |
Gbps |
GXT clock lines | 26.6 | N/A | N/A | 4 GXT channels within the same transceiver bank and 2 from the bank above or 2 from the bank below. 82 | Gbps |
Symbol/Description | Condition | Transceiver Speed Grade 3 | Unit | ||
---|---|---|---|---|---|
Min | Typ | Max | |||
Supported I/O Standards | — | High Speed Differential I/O, CML, Differential LVPECL, and LVDS | |||
Absolute VMAX for a receiver pin 83 | — | — | — | 1.2 | V |
Absolute VMIN for a receiver pin 83 84 | — | -0.4 | — | — | V |
Maximum peak-to-peak differential input voltage VID (diff p-p) | VCCR_GXB = 1.03 V 85 | — | — | 2.0 | V |
Differential on-chip termination resistors | 85-Ω setting | — | 85 ± 20% | — | Ω |
100-Ω setting | — | 100 ± 20% | — | Ω | |
VICM (AC coupled) | VCCR_GXB = 1.03 V | — | 700 | — | mV |
VCCR_GXB = 1.12 V | — | 750 | — | mV | |
tLTR 86 | — | — | — | 1 | ms |
tLTD 87 | — | 4 | — | — | µs |
tLTD_manual 88 | — | 4 | — | — | µs |
tLTR_LTD_manual 89 | — | 15 | — | — | µs |
Run Length | — | — | — | 200 | UI |
CDR ppm tolerance | PCIe-only | -300 | — | 300 | ppm |
All other protocols | -1000 | — | 1000 | ppm |
Symbol/Description | Condition | Transceiver Speed Grade 2 and 3 | Unit | ||
---|---|---|---|---|---|
Min | Typ | Max | |||
Supported I/O Standards | — | High Speed Differential I/O 90 | — | ||
Differential on-chip termination resistors | 85-Ω setting | — | 85 ± 20% | — | Ω |
100-Ω setting | — | 100 ± 20% | — | Ω | |
VOCM (AC coupled) | VCCT_GXB = 1.03 V | — | 515 | — | mV |
Rise time 91 | 20% to 80% | 20 | — | 130 | ps |
Fall time 91 | 80% to 20% | 20 | — | 130 | ps |
Intra-differential pair skew | TX VCM = 0.5 V and slew rate of 15 ps | — | — | 15 92 | ps |
Symbol | VOD Setting 93 | VOD/VCCT_GXB Ratio |
---|---|---|
VOD differential value = VOD/VCCT_GXB ratio x VCCT_GXB | 31 | 1.00 |
30 | 0.97 | |
29 | 0.93 | |
28 | 0.90 | |
27 | 0.87 | |
26 | 0.83 | |
25 | 0.80 | |
24 | 0.77 | |
23 | 0.73 | |
22 | 0.70 | |
21 | 0.67 | |
20 | 0.63 | |
19 | 0.60 | |
18 | 0.57 | |
17 | 0.53 | |
16 | 0.50 | |
15 | 0.47 | |
14 | 0.43 | |
13 | 0.40 | |
12 | 0.37 |
|
Clock | Value | Unit |
---|---|---|
reconfig_clk | ≤ 150 | MHz |
fixed_clk for the RX detect circuit | 250 ± 20% | MHz |
For OSC_CLK_1 specifications, refer to the External Configuration Clock Source Requirements section.
H-Tile Transceiver Performance Specifications
Transceiver Performance for Intel Stratix 10 GX/SX/MX/TX H-Tile Devices
Symbol | Description | Transceiver Speed Grade | ||
---|---|---|---|---|
-1 | -2 | -3 | ||
GX channels | Chip-to-chip and Backplane | 17.4 Gbps | ||
GXT channels | Chip-to-chip and Backplane | 28.3 Gbps 95 | 26.6 Gbps | N/A |
Symbol/Description | Condition | Transceiver Speed Grade 1 | Transceiver Speed Grade 2 | Transceiver Speed Grade 3 | Unit |
---|---|---|---|---|---|
Supported Output Frequency | Maximum Frequency | 14.15 | 13.3 | 8.7 | GHz |
Minimum Frequency | 500 | MHz | |||
tLOCK 96 | Maximum Frequency | 1 | ms | ||
tARESET 97 | — | 25 | Avalon Clock Cycles |
Symbol/Description | Condition | Mode | All Transceiver Speed Grades | Unit |
---|---|---|---|---|
Supported Output Frequency (VCO frequency based) | Maximum datarate | Transceiver - HDMI | 12.5 | Gbps |
Transceiver - General | 12.5 | |||
Transceiver - OTN, SDI Cascade | 14.025 | |||
Minimum datarate | Transceiver - HDMI | 4.6 | Gbps | |
Transceiver - General | 6 | |||
Transceiver - OTN, SDI Cascade | 7 | |||
tLOCK 96 | Maximum Frequency | 1 | ms | |
tARESET 97 | — | 25 | Avalon Clock Cycles |
Transceiver Specifications for Intel Stratix 10 GX/SX H-Tile Devices
Symbol/Description | Condition | Min | Typ | Max | Unit |
---|---|---|---|---|---|
Supported I/O Standards | Dedicated reference clock pin | CML, Differential LVPECL, LVDS, and HCSL | |||
RX reference clock pin | CML, Differential LVPECL, and LVDS | ||||
Input Reference Clock Frequency (CMU PLL) |
50 | — | 800 | MHz | |
Input Reference Clock Frequency (ATX PLL) |
100 | — | 800 | MHz | |
Input Reference Clock Frequency (fPLL PLL) |
25 98/50 | — | 800 | MHz | |
Rise time | 20% to 80% | — | — | 350 | ps |
Fall time | 80% to 20% | — | — | 350 | ps |
Duty cycle | — | 45 | — | 55 | % |
Spread-spectrum modulating clock frequency | PCIe | 30 | — | 33 | kHz |
Spread-spectrum downspread | PCIe | — | 0 to –0.5 | — | % |
On-chip termination resistors | — | — | 100 | — | Ω |
Absolute VMAX | Dedicated reference clock pin | — | — | 1.6 | V |
RX reference clock pin | — | — | 1.2 | V | |
Absolute VMIN | — | –0.4 | — | — | V |
Peak-to-peak differential input voltage | — | 200 | — | 1600 | mV |
VICM (AC coupled) | VCCR_GXB =1.03 V | — | 0 | — | V |
VCCR_GXB = 1.12 V | — | 0 | — | V | |
VICM (DC coupled) | HCSL I/O standard for PCIe reference clock | 250 | — | 550 | mV |
Transmitter REFCLK Phase Noise (800 MHz) 99 100 | 100 Hz | — | — | –70 | dBc/Hz |
1 kHz | — | — | –90 | dBc/Hz | |
10 kHz | — | — | –100 | dBc/Hz | |
100 kHz | — | — | –110 | dBc/Hz | |
≥ 1 MHz | — | — | –120 | dBc/Hz | |
RREF | — | — | 2.0 k ±1% | — | Ω |
TSSC-MAX-PERIOD-SLEW | Max SSC df/dt | 0.75 |
Clock Network | Maximum Performance 101 | Channel Span | Unit | ||
---|---|---|---|---|---|
ATX | fPLL | CMU | |||
x1 | 17.4 | 12.5 | 10.3125 | 6 channels | Gbps |
x6 | 17.4 | 12.5 | N/A | 6 channels | Gbps |
x24 | 17.4 105 | 12.5 | N/A |
2 banks up and 1 bank down (total 24 channels) or 2 banks down and 1 bank up (total 24 channels) |
Gbps |
GXT clock lines | 28.3 | N/A | N/A | 4 GXT channels within the same transceiver bank and 2 from the bank above or 2 from the bank below. 102 | Gbps |
Symbol/Description | Condition | All Transceiver Speed Grades | Unit | ||
---|---|---|---|---|---|
Min | Typ | Max | |||
Supported I/O Standards | — | High Speed Differential I/O, CML, Differential LVPECL, and LVDS | |||
Absolute VMAX for a receiver pin 103 | — | — | — | 1.2 | V |
Absolute VMIN for a receiver pin 104 | — | -0.4 | — | — | V |
Maximum peak-to-peak differential input voltage VID (diff p-p) before device configuration | — | — | — | 2.0 | V |
Maximum peak-to-peak differential input voltage VID (diff p-p) after device configuration | VCCR_GXB = 1.03 V, 1.12 V 105, 106 | — | — | 2.0 | V |
Differential on-chip termination resistors | 85-Ω setting | — | 85 ± 20% | — | Ω |
100-Ω setting | — | 100 ± 20% | — | Ω | |
VICM (AC coupled) | VCCR_GXB = 1.03 V 106 | — | 700 | — | mV |
VCCR_GXB = 1.12 V 106 | — | 750 | — | mV | |
tLTR 107 | — | — | — | 1 | ms |
tLTD 108 | — | 4 | — | — | µs |
tLTD_manual 109 | — | 4 | — | — | µs |
tLTR_LTD_manual 110 | — | 15 | — | — | µs |
Run Length | — | — | — | 200 | UI |
CDR ppm tolerance | PCIe-only | -300 | — | 300 | ppm |
All other protocols | -1000 | — | 1000 | ppm |
Symbol/Description | Condition | Transceiver Speed Grade 3 | Unit | ||
---|---|---|---|---|---|
Min | Typ | Max | |||
Supported I/O Standards | — | High Speed Differential I/O 111 | — | ||
Differential on-chip termination resistors | 85-Ω setting | — | 85 ± 20% | — | Ω |
100-Ω setting | — | 100 ± 20% | — | Ω | |
VOCM (AC coupled) | VCCT_GXB = 1.03 V 112 | — | 515 | — | mV |
VOCM (AC coupled) | VCCT_GXB = 1.12 V 112 | — | 560 | — | mV |
VOCM (DC coupled) 113 | VCCT_GXB = 1.03 V 112 | — | 515 | — | mV |
VOCM (DC coupled) 113 | VCCT_GXB = 1.12 V 112 | — | 560 | — | mV |
Rise time 114 | 20% to 80% | 20 | — | 130 | ps |
Fall time 114 | 80% to 20% | 20 | — | 130 | ps |
Intra-differential pair skew | TX VCM = 0.5 V and slew rate of 15 ps | — | — | 15 115 | ps |
Symbol | VOD Setting 116 | VOD/VCCT_GXB Ratio |
---|---|---|
VOD differential value = VOD/VCCT_GXB ratio x VCCT_GXB | 31 | 1.00 |
30 | 0.97 | |
29 | 0.93 | |
28 | 0.90 | |
27 | 0.87 | |
26 | 0.83 | |
25 | 0.80 | |
24 | 0.77 | |
23 | 0.73 | |
22 | 0.70 | |
21 | 0.67 | |
20 | 0.63 | |
19 | 0.60 | |
18 | 0.57 | |
17 | 0.53 | |
16 | 0.50 | |
15 | 0.47 | |
14 | 0.43 | |
13 | 0.40 | |
12 | 0.37 |
|
Clock | Value | Unit |
---|---|---|
reconfig_clk | ≤ 150 | MHz |
fixed_clk for the RX detect circuit | 250 ± 20% | MHz |
For OSC_CLK_1 specifications, refer to the External Configuration Clock Source Requirements section.
E-Tile Transceiver Performance Specifications
Transceiver Performance for Intel Stratix 10 E-Tile Devices
Transceiver Reference Clock Specifications
Symbol | Refclk Parameter | Minimum | Typical | Maximum | Unit |
---|---|---|---|---|---|
VTT | Termination Voltage (2.5V compliant) | 0.4 | 0.5 | 0.6 | V |
VTT | Termination Voltage (3.3V compliant) | 1.04 | 1.3 | 1.56 | V |
RTT | Termination Resistor | 40 | 50 | 60 | Ohm |
VDIFF | Differential Voltage | 0.4 | 0.8 | 1.2 | V |
VCM | Input Common Mode Voltage (2.5V compliant, no internal termination resistor) | VDIFF/2 | VCCCLK_GXE-VDIFF/2 | V | |
VCM | Input Common Mode Voltage (2.5V compliant, internal termination resistor) | VCCCLK_GXE - 1.6 | VCCCLK_GXE - 1.3 | VCCCLK_GXE - 1.0 | V |
VCM | Input Common Mode Voltage (3.3V compliant, no internal termination resistor) | VDIFF/2 | VCCCLK_GXE-VDIFF/2 | V | |
VCM | Input Common Mode Voltage (3.3V compliant, internal termination resistor) | 1.4 | 2 | 2.6 | V |
Parameter | Condition | Minimum | Typical | Maximum | Unit |
---|---|---|---|---|---|
Frequency | - | 125 | 156.25 | 700 | MHz |
Frequency Tolerance | - | -100 | 100 | PPM | |
Clock Duty Cycle | - | 45 | 50 | 55 | % |
Rise & Fall Times | 20% - 80% | 40 | 300 | ps | |
Phase Jitter | 12 KHz - 20 MHz | 0.375 | 0.5 | ps rms | |
Phase Noise 120 | 10 KHz | -130 | dBc/Hz | ||
100 KHz | -138 | dBc/Hz | |||
500 KHz | -138 | dBc/Hz | |||
3 MHz | -140 | dBc/Hz | |||
10 MHz | -144 | dBc/Hz | |||
20 MHz | -146 | dBc/Hz |
Transmitter Specifications for Intel Stratix 10 E-Tile Devices
Symbol/Description | Condition | Minimum | Typical | Maximum | Unit |
---|---|---|---|---|---|
Transmitter differential output voltage peak-to-peak | No precursor/postcursor de-emphasis | 0.965 | V | ||
Transmitter common mode voltage | VCCRT_GXE/2 | V |
Receiver Specifications for Intel Stratix 10 E-Tile Devices
Symbol/Description | Condition | Minimum | Typical | Maximum | Unit |
---|---|---|---|---|---|
Supported I/O Standards | — | LVPECL | — | ||
Absolute VMAX for a receiver pin122 | NRZ | — | VCCH_GXE + 0.3 | — | V |
PAM4 | — | VCCH_GXE | — | V | |
Maximum peak-to-peak differential input voltage VID (diff p-p) before/after device configuration122 | — | 1.2 | V | ||
VCM (AC coupled)121 122 | NRZ | GND | — | VCCH_GXE | V |
PAM4 | GND + 0.3 | — | VCCH_GXE – 0.3 | V | |
Receiver run length123 | — | — | — | 100124 | symbols |
DC input impedance | — | 40 | — | 60 | Ω |
DC differential input impedance | — | 80 | 100 | 120 | Ω |
Powered down DC input impedance | Receiver pin impedance when the receiver termination is powered down | 100k | — | — | Ω |
Differential termination | From DC to 100 MHz | 80 | 100 | 120 | Ω |
PPM tolerance | Allowed frequency mismatch between REFCLK and RX data | — | — | 750 | ppm |
- RX inputs have external AC coupling capacitors of at least 100 nF.
- The absolute voltage applied to the RX+ and RX- pins should not exceed ±300 mV (for a total of 600 mV p-p) (single ended).
- The total differential voltage (combination of RX+/RX-) should not exceed 1,200 mV.
- The transceiver termination selection must be external AC coupling (during mission mode).
P-Tile Transceiver Performance Specifications
Transceiver Performance for Intel Stratix 10 DX P-Tile Devices
Symbol/Description | Condition | Gen 1 | Gen 2 | Gen 3 | Gen 4 | Unit |
---|---|---|---|---|---|---|
Supported data rate125 | PCIe* | 2.5 | 5 | 8 | 16 | Gbps |
Symbol/Description | Condition | Min | Typ | Max | Unit |
---|---|---|---|---|---|
VCO frequency | PCIe* | — | 5 | — | GHz |
Intel® UPI 126 | — | 5.2 | — | GHz | |
PLL bandwidth (BWTX_PKG_PLL1) 127 | PCIe* 2.5 GT/s | 1.5 | — | 22 | MHz |
PCIe* 5.0 GT/s | 8 | — | 16 | MHz | |
PLL bandwidth (BWTX_PKG_PLL2)127 | PCIe* 5.0 GT/s | 5 | — | 16 | MHz |
PLL peaking (PKGTX_PLL1) | PCIe* 2.5 GT/s | — | — | 3 | dB |
PCIe* 5.0 GT/s | — | — | 3 | dB | |
PLL peaking (PKGTX_PLL2)127 | PCIe* 5.0 GT/s | 1 | — | — | dB |
Symbol/Description | Condition | Min | Typ | Max | Unit |
---|---|---|---|---|---|
VCO frequency | PCIe* | — | 8 | — | GHz |
PLL bandwidth (BWTX-PKG_PLL1) 128 | PCIe* 8.0 GT/s | 2 | — | 4 | MHz |
PCIe* 16.0 GT/s | 2 | — | 4 | MHz | |
PLL bandwidth (BWTX-PKG_PLL2)128 | PCIe* 8.0 GT/s | 2 | — | 5 | MHz |
PCIe* 16.0 GT/s | 2 | — | 5 | MHz | |
PLL peaking (PKGTX-PLL1)128 | PCIe* 8.0 GT/s | — | — | 2 | dB |
PCIe* 16.0 GT/s | — | — | 2 | dB | |
PLL peaking (PKGTX-PLL2)128 | PCIe* 8.0 GT/s | — | — | 1 | dB |
PCIe* 16.0 GT/s | — | — | 1 | dB |
Transceiver Reference Clock Specifications
Symbol/Description | Condition | Min | Typ | Max | Unit |
---|---|---|---|---|---|
Supported I/O standards | — | HCSL | — | ||
Input reference clock frequency 129 | — | 99.97 | 100 | 100.03 | MHz |
Rising edge rate 130 | PCIe* | 0.6 | — | 4 | V/ns |
Falling edge rate130 | PCIe* | 0.6 | — | 4 | V/ns |
Duty cycle | PCIe* | 40 | — | 60 | % |
Spread-spectrum modulating clock frequency | — | 30 | — | 33 | kHz |
Spread-spectrum downspread | — | –0.5 | — | 0 | % |
Absolute VMAX | — | — | — | 1.15 | V |
Absolute VMIN | — | — | — | –0.3 | V |
Peak-to-peak differential input voltage | — | 300 | — | 1,500 | mV |
VICM (DC coupled) | HCSL I/O standard for PCIe* reference clock | 250 | — | 550 | mV |
Cycle to cycle jitter (TCCJITTER) 131 | PCIe* | — | — | 150 | ps |
TSSC-MAX-PERIOD-SLEW | Max SSC df/dt | — | — | 1,250 | ppm/us |
Transmitter Specification for Intel Stratix 10 DX P-Tile Devices
Symbol/Description | Condition | Min | Typ | Max | Unit |
---|---|---|---|---|---|
Supported I/O standards | — | High Speed Differential I/O | — | ||
Differential on-chip termination resistors | PCIe | 80 | — | 120 | Ω |
Differential peak-to-peak voltage for full swing | PCIe 2.5 GT/s | 800 | — | 1,100 | mV |
PCIe 5.0 GT/s | 800 | — | 1,100 | mV | |
PCIe 8.0 GT/s | 800 | — | 1,100 | mV | |
PCIe 16.0 GT/s | 800 | — | 1,100 | mV | |
Differential peak-to-peak voltage during EIEOS | PCIe 8.0 GT/s and 16.0 GT/s | 250 | — | — | mV |
Lane-to-lane output skew | PCIe 2.5 GT/s | — | — | 2.5 | ns |
PCIe 5.0 GT/s | — | — | 2 | ns | |
PCIe 8.0 GT/s | — | — | 1.5 | ns | |
PCIe 16.0 GT/s | — | — | 1.25 | ns | |
Intel® UPI 132 | — | — | 5 | UI |
Receiver Specifications for Intel Stratix 10 DX P-Tile Devices
Symbol/Description | Condition | Min | Typ | Max | Unit |
---|---|---|---|---|---|
Supported I/O Standards | — | High Speed Differential I/O | — | ||
Peak-to-peak differential input voltage VID (diff p-p) | PCIe* 2.5 GT/s 133 | 0.175 | — | 1.2 | V |
PCIe* 5.0 GT/s 133 | 0.1 | — | 1.2 | V | |
PCIe* 8.0 GT/s | 25 134 | — | — 135 | mV | |
PCIe* 16.0 GT/s | 15 134 | — | — 135 | mV | |
Differential on-chip termination resistors | — | 80 | — | 120 | Ω |
RESREF 136 | — | 167.3 | 169 | 170.7 | Ω |
RREF | — | 2.772 | 2.8 | 2.828 | kΩ |
HPS Performance Specifications
This section provides hard processor system (HPS) specifications and timing for Intel® Stratix® 10 devices.
HPS Clock Performance
Performance | VCCL_HPS (V) | MPU Frequency (MHz) | SDRAM Interconnect Frequency137 (MHz) | L3 Interconnect Frequency (MHz) |
---|---|---|---|---|
–E1V, –I1V | SmartVID | 1,200 | 533 | 400 |
0.9 | 1,200 | 533 | 400 | |
0.94 | 1,350 | 533 | 400 138 | |
–E2V, –I2V | SmartVID | 1,000 | 467 | 400 |
0.9 | 1,000 | 467 | 400 | |
0.94 | 1,000 | 467 | 400 | |
–E3V, –I3V | SmartVID | 800 | 400 | 333 |
0.9 | 800 | 400 | 333 | |
0.94 | 800 | 400 | 400 | |
–E2L, –I2L 139 | 0.9 | 1200 | 467 | 400 |
0.94 | 1,350 | 467 | 400 138 | |
–E3X, –I3X 139 | 0.9 | 1,200 | 400 | 400 |
0.94 | 1,350 | 400 | 400 138 |
Note that VCCL_HPS can not be connected to SmartVID for –E2L, –I2L, –E3X, and –I3X devices.
HPS Internal Oscillator Frequency
Description | Min | Typ | Max | Unit |
---|---|---|---|---|
Internal Oscillator Frequency | 100 | 200 | 300 | MHz |
HPS PLL Specifications
HPS PLL Input Requirements
Description | Min | Typ | Max | Unit |
---|---|---|---|---|
Clock input range | 25 | — | 125 | MHz |
Clock input accuracy | — | — | 50 | PPM |
Clock input duty cycle | 45 | 50 | 55 | % |
HPS PLL Performance
HPS Cold Reset
HPS SPI Timing Characteristics
Symbol | Description | Min | Typ | Max | Unit |
---|---|---|---|---|---|
Tspi_ref_clk | The period of the SPI internal reference clock, sourced from l4_main_clk | 2.5 | — | — | ns |
Tclk | SPIM_CLK clock period | 16.67 | — | — | ns |
Tdutycycle | SPIM_CLK duty cycle | 45 | 50 | 55 | % |
Tck_jitter | SPIM_CLK output jitter | — | — | 2 | % |
Tdio | Master-out slave-in (MOSI) output skew | –3 | — | 2 | ns |
Tdssfrst 142 | SPI_SS_N asserted to first SPIM_CLK edge | (1.5 × Tclk) – 2 | — | — | ns |
Tdsslst 142 | Last SPIM_CLK edge to SPI_SS_N deasserted | Tclk – 2 | — | — | ns |
Tsu 143 | SPIM_MISO setup time with respect to SPIM_CLK capture edge | 4.5 – (rx_sample_dly × T spi_ref_clk) 144 | — | — | ns |
Th 143 | Input hold in respect to SPIM_CLK capture edge | 1.3 + (rx_sample_dly× Tspi_ref_clk) | — | — | ns |
Symbol | Description | Min | Typ | Max | Unit |
---|---|---|---|---|---|
Tspi_ref_clk | The period of the SPI internal reference clock, sourced from l4_main_clk | 2.5 | — | — | ns |
Tclk | SPIM_CLK clock period | 30 | — | — | ns |
Tdutycycle | SPIM_CLK duty cycle | 45 | 50 | 55 | % |
Td | Master-in slave-out (MISO) output skew | (2 × Tspi_ref_clk) + 3 | — | (3 × Tspi_ref_clk) + 11 | ns |
Tsu | Master-out slave-in (MOSI) setup time | 4 | — | — | ns |
Th | Master-out slave-in (MOSI) hold time | 9 | — | — | ns |
Tsuss | SPI_SS_N asserted to first SPIM_CLK edge | Tspi_ref_clk + 4 | — | — | ns |
Thss | Last SPIM_CLK edge to SPI_SS_N deasserted | Tspi_ref_clk + 4 | — | — | ns |
HPS SD/MMC Timing Characteristics
Symbol | Description | Min | Typ | Max | Unit |
---|---|---|---|---|---|
Tsdmmc_cclk | SDMMC_CCLK clock period (Identification mode) | 2500 | — | — | ns |
SDMMC_CCLK clock period (SDR12) | 40 | — | — | ns | |
SDMMC_CCLK clock period (SDR25) | 20 | — | — | ns | |
Tdutycycle | SDMMC_CCLK duty cycle | 45 | 50 | 55 | % |
Tsdmmc_cclk_jitter | SDMMC_CCLK output jitter | — | — | 2 | % |
Tsdmmc_clk | Internal reference clock before division by 4 | 5 | — | — | ns |
Td | SDMMC_CMD/SDMMC_DATA[7:0] output delay 145 | Tsdmmc_clk × drvsel/2 | — | 3 + (Tsdmmc_clk × drvsel/2) | ns |
Tsu | SDMMC_CMD/SDMMC_DATA[7:0] input setup 146 | 6 – (Tsdmmc_clk × smplsel/2) | — | — | ns |
Th | SDMMC_CMD/SDMMC_DATA[7:0] input hold 146 | 0.5 + (Tsdmmc_clk × smplsel/2) | — | — | ns |
None of the HPS I/Os supports 3 V mode, while SD/MMC cards must operate at 3 V at power on. eMMC devices can operate at 1.8 V at power on.
HPS USB UPLI Timing Characteristics
Symbol | Description | Min | Typ | Max | Unit |
---|---|---|---|---|---|
Tusb_clk | USB_CLK clock period | — | 16.667 | — | ns |
Td | Clock to USB_STP/USB_DATA[7:0] output delay | 2 | — | 7 | ns |
Tsu | Setup time for USB_DIR/USB_NXT/USB_DATA[7:0] | 4 | — | — | ns |
Th | Hold time for USB_DIR/USB_NXT/USB_DATA[7:0] | 1 | — | — | ns |
HPS Ethernet Media Access Controller (EMAC) Timing Characteristics
Symbol | Description | Min | Typ | Max | Unit |
---|---|---|---|---|---|
Tclk (1000Base-T) | TX_CLK clock period | — | 8 | — | ns |
Tclk (100Base-T) | TX_CLK clock period | — | 40 | — | ns |
Tclk (10Base-T) | TX_CLK clock period | — | 400 | — | ns |
Tdutycycle (1000Base-T) | TX_CLK duty cycle | 45 | 50 | 55 | % |
Tdutycycle(10/100Base-T) | TX_CLK duty cycle | 40 | 50 | 60 | % |
Td 147 |
TXD/TX_CTL to TX_CLK output skew | –0.5 | — | 0.5 | ns |
Symbol | Description | Min | Typ | Max | Unit |
---|---|---|---|---|---|
Tclk (1000Base-T) | RX_CLK clock period | — | 8 | — | ns |
Tclk (100Base-T) | RX_CLK clock period | — | 40 | — | ns |
Tclk (10Base-T) | RX_CLK clock period | — | 400 | — | ns |
Tdutycycle(1000Base-T) | RX_CLK duty cycle | 45 | 50 | 55 | % |
Tdutycycle(10/100Base-T) | RX_CLK duty cycle | 40 | 50 | 60 | % |
Tsu | RX_D/RX_CTL to RX_CLK setup time | 1 | — | — | ns |
Th 149 | RX_CLK to RX_D/RX_CTL hold time | 1 | — | — | ns |
Symbol | Description | Min | Typ | Max | Unit |
---|---|---|---|---|---|
Tclk | REF_CLK clock period, sourced by HPS TX_CLK | — | 20 | — | ns |
REF_CLK clock period, sourced by external clock source | — | 20 | — | ns | |
Tdutycycle_int | Clock duty cycle, REF_CLK sourced by TX_CLK | 35 | 50 | 65 | % |
Tdutycycle_ext | Clock duty cycle, REF_CLK sourced by external clock source | 35 | 50 | 65 | % |
Symbol | Description | Min | Typ | Max | Unit |
---|---|---|---|---|---|
Td | TX_CLK to TXD/TX_CTL output data delay | 2 | — | 10 | ns |
Symbol | Description | Min | Typ | Max | Unit |
---|---|---|---|---|---|
Tsu | RX_D/RX_CTL setup time | 2 | — | — | ns |
Th | RX_D/RX_CTL hold time | 1 | — | — | ns |
Symbol | Description | Min | Typ | Max | Unit |
---|---|---|---|---|---|
Tclk | MDC clock period | 400 | — | — | ns |
Td | MDC to MDIO output data delay | 10 | — | 300 | ns |
Tsu | Setup time for MDIO data | 10 | — | — | ns |
Th | Hold time for MDIO data | 0 | — | — | ns |
If you connect a PHY that does not implement clock-to-data skew, you can meet the HPS EMAC’s 1 ns setup time by delaying RX_CLK by 1.5-2 ns, using the HPS I/O programmable delay.
HPS I2C Timing Characteristics
Symbol | Description | Standard Mode | Fast Mode | Unit | ||
---|---|---|---|---|---|---|
Min | Max | Min | Max | |||
Tclk | Serial clock (SCL) clock period | 10 | — | 2.5 | — | μs |
Tclk_jitter | I2C clock output jitter | — | 2 | — | 2 | % |
THIGH 150 | SCL high period | 4 151 | — | 0.6 152 | — | μs |
TLOW 153 | SCL low period | 4.7 154 | — | 1.3 155 | — | μs |
TSU;DAT | Setup time for serial data line (SDA) data to SCL | 0.25 | — | 0.1 | — | μs |
THD;DAT 156 | Hold time for SCL to SDA data | 0 | 3.15 | 0 | 0.6 | μs |
TVD;DAT and TVD;ACK 157 | SCL to SDA output data delay | — | 3.45 158 | — | 0.9 159 | μs |
TSU;STA | Setup time for a repeated start condition | 4.7 | — | 0.6 | — | μs |
THD;STA | Hold time for a repeated start condition | 4 | — | 0.6 | — | μs |
TSU;STO | Setup time for a stop condition | 4 | — | 0.6 | — | μs |
TBUF | SDA high pulse duration between STOP and START | 4.7 | — | 1.3 | — | μs |
Tscl:r 160 | SCL rise time | — | 1000 | 20 | 300 | ns |
Tscl:f 160 | SCL fall time | — | 300 | 6.54 | 300 | ns |