Intel Stratix 10 Device Datasheet

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S10-DATASHEET | 2019.02.25

Intel Stratix 10 Device Datasheet

This datasheet describes the electrical characteristics, switching characteristics, configuration specifications, and timing for Intel^® Stratix^® 10 devices.

Table 1. Intel^® Stratix^® 10 Device Grades and Speed Grades Supported
Device Grade	Speed Grade Supported
Extended	–E1V (fastest) –E2V –E2L –E3V –E3X
Industrial	–I1V –I2V –I2L –I3V –I3X

The suffix after the speed grade denotes the power options offered in Intel^® Stratix^® 10 devices.

V—SmartVID with standard static power
L—0.85 V fixed voltage with low static power
X—0.85 V fixed voltage with lowest static power

Table 2. Datasheet Status for Intel^® Stratix^® 10 Devices
Variant	Datasheet Status
Intel^® Stratix^® 10 GX	Final
Intel^® Stratix^® 10 SX	Final
Intel^® Stratix^® 10 TX	Final
Intel^® Stratix^® 10 MX	Final

Electrical Characteristics

The following sections describe the operating conditions and power consumption of Intel^® Stratix^® 10 devices.

Operating Conditions

Intel^® Stratix^® 10 devices are rated according to a set of defined parameters. To maintain the highest possible performance and reliability of the Intel^® Stratix^® 10 devices, you must consider the operating requirements described in this section.

Absolute Maximum Ratings

This section defines the maximum operating conditions for Intel^® Stratix^® 10 devices. The values are based on experiments conducted with the devices and theoretical modeling of breakdown and damage mechanisms. The functional operation of the device is not implied for these conditions.

CAUTION:

Conditions outside the range listed in the following table may cause permanent damage to the device. Additionally, device operation at the absolute maximum ratings for extended periods of time may have adverse effects on the device.

Table 3. Absolute Maximum Ratings for Intel^® Stratix^® 10 Devices
Symbol	Description	Condition	Minimum	Maximum	Unit
V_CC	Core voltage power supply	—	–0.50	1.26	V
V_CCP	Periphery circuitry and transceiver fabric interface power supply	—	–0.50	1.26	V
V_CCERAM	Embedded memory and digital transceiver power supply	—	–0.50	1.24	V
V_CCPT	Power supply for programmable power technology and I/O pre-driver	—	–0.50	2.46	V
V_CCBAT	Battery back-up power supply for design security volatile key register	—	–0.50	2.46	V
V_{CCIO_SDM}	Configuration pins power supply	—	–0.50	2.19	V
V_CCIO	I/O buffers power supply	3 V I/O	–0.50	4.10	V
V_CCIO	I/O buffers power supply	LVDS I/O ¹	–0.50	2.19	V
V_{CCA_PLL}	Phase-locked loop (PLL) analog power supply	—	–0.50	2.46	V
V_{CCT_GXB}	Transmitter analog power supply	—	–0.50	1.47	V
V_{CCR_GXB}	Receiver analog power supply	—	–0.50	1.47	V
V_{CCH_GXB}	Transmitter output buffer power supply	—	–0.50	2.46	V
V_{CCL_HPS}	HPS core voltage and periphery circuitry power supply	—	–0.50	1.30	V
V_{CCIO_HPS}	HPS I/O buffers power supply	LVDS I/O ¹	–0.50	2.19	V
V_{CCPLL_HPS}	HPS PLL power supply	—	–0.50	2.46	V
V_I	DC input voltage	3 V I/O	–0.30	3.80	V
V_I	DC input voltage	LVDS I/O	–0.30	2.19	V
I_OUT	DC output current per pin	—	–15 ² ³ ⁴ ⁵ ⁶	15	mA
T_J	Absolute junction temperature for Intel^® Stratix^® 10 MX devices	—	–55	120	°C
T_J	Absolute junction temperature for all other Intel^® Stratix^® 10 devices	—	-55	125	°C
T_STG	Storage temperature (no bias) for Intel^® Stratix^® 10 MX devices	—	–55	120	°C
T_STG	Storage temperature (no bias) for all other Intel^® Stratix^® 10 devices	—	-55	150	°C

¹ The LVDS I/O values are applicable to all dedicated and dual-function configuration I/Os.

² The maximum current allowed through any LVDS I/O bank pin when the device is not turned on or during power-up/power-down conditions is 10 mA.

³ Total current per LVDS I/O bank must not exceed 100 mA.

⁴ Voltage level must not exceed 1.89 V.

⁵ Applies to all I/O standards and settings supported by LVDS I/O banks, including single-ended and differential I/Os.

⁶ Applies only to LVDS I/O banks. 3 V I/O banks are not covered under this specification and must be implemented as per the power sequencing requirement. For more details, refer to AN 692: Power Sequencing Considerations for Intel^® Cyclone^® 10 GX, Intel^® Arria^® 10, and Intel^® Stratix^® 10 Devices and Intel^® Stratix^® 10 Power Management User Guide.

Maximum Allowed Overshoot and Undershoot Voltage

During transitions, input signals may overshoot to the voltage listed in the following table and undershoot to –1.1 V for input currents less than 100 mA and periods shorter than 20 ns.

The maximum allowed overshoot duration is specified as a percentage of high time over the lifetime of the device. A DC signal is equivalent to 100% duty cycle.

For example, when using V_CCIO = 1.8 V, a signal that overshoots to 2.44 V for LVDS I/O can only be at 2.44 V for ~6% over the lifetime of the device.

Table 4. Maximum Allowed Overshoot During Transitions for Intel^® Stratix^® 10 Devices (for LVDS I/O)This table lists the maximum allowed input overshoot voltage and the duration of the overshoot voltage as a percentage of device lifetime.
Symbol	Description	LVDS I/O (V) ⁷	Overshoot Duration as % at T_J = 100°C	Unit
Vi (AC)	AC input voltage	V_CCIO + 0.30	100	%
		V_CCIO + 0.35	60	%
		V_CCIO + 0.40	30	%
		V_CCIO + 0.45	20	%
		V_CCIO + 0.50	10	%
		V_CCIO + 0.55	6	%
		> V_CCIO + 0.55	No overshoot allowed	%

Table 5. Maximum Allowed Overshoot During Transitions for Intel^® Stratix^® 10 Devices (for 3 V I/O)This table lists the maximum allowed input overshoot voltage and the duration of the overshoot voltage as a percentage of device lifetime.
Symbol	Description	3 V I/O (V)	Overshoot Duration as % at T_J = 100°C	Unit
Vi (AC)	AC input voltage	V_CCIO + 0.65	100	%
		V_CCIO + 0.70	42	%
		V_CCIO + 0.75	18	%
		V_CCIO + 0.80	9	%
		V_CCIO + 0.85	4	%
		> V_CCIO + 0.85	No overshoot allowed	%

For an overshoot of 2.5 V, the percentage of high time for the overshoot can be as high as 100% over a 10-year period. Percentage of high time is calculated as ([delta T]/T) × 100. This 10-year period assumes that the device is always turned on with 100% I/O toggle rate and 50% duty cycle signal.

Figure 1. Intel^® Stratix^® 10 Devices Overshoot Duration

⁷ The LVDS I/O values are applicable to all dedicated and dual-function configuration I/Os.

Recommended Operating Conditions

This section lists the functional operation limits for the AC and DC parameters for Intel^® Stratix^® 10 devices.

Recommended Operating Conditions

Table 6. Recommended Operating Conditions for Intel^® Stratix^® 10 DevicesThis table lists the steady-state voltage values expected for Intel^® Stratix^® 10 devices. Power supply ramps must all be strictly monotonic, without plateaus.
Symbol	Description	Condition	Minimum ⁸	Typical	Maximum ⁸	Unit
V_CC	Core voltage power supply	–E1V, –I1V, –E2V, –I2V, –E3V, –I3V ⁹	(Typical) – 30 mV	0.8 – 0.94	(Typical) + 30 mV	V
V_CC	Core voltage power supply	–E2L, –I2L, –E3X, –I3X	0.82	0.85	0.88	V
V_CCP	Periphery circuitry and transceiver fabric interface power supply	–E1V, –I1V, –E2V, –I2V, –E3V, –I3V ⁹	(Typical) – 30 mV	0.8 – 0.94	(Typical) + 30 mV	V
V_CCP		–E2L, –I2L, –E3X, –I3X	0.82	0.85	0.88	V
V_{CCIO_SDM}	Configuration pins power supply	1.8 V	1.71	1.8	1.89	V
V_{CCPLLDIG_SDM}	Secure Device Manager (SDM) block PLL digital power supply	—	0.87	0.9	0.93	V
V_{CCPLL_SDM}	SDM block PLL analog power supply	—	1.71	1.8	1.89	V
V_{CCFUSEWR_SDM}	Fuse block writing power supply	—	2.35	2.4	2.45	V
V_CCADC	ADC voltage sensor power supply	—	1.71	1.8	1.89	V
V_CCERAM	Embedded memory and digital transceiver power supply	0.9 V	0.87	0.9	0.93	V
V_CCBAT ¹⁰	Battery back-up power supply (For design security volatile key register)	—	1.2	—	1.8	V
V_CCPT	Power supply for programmable power technology and I/O pre-driver	1.8 V	1.71	1.8	1.89	V
V_CCIO	I/O buffers power supply	3.0 V (for 3 V I/O only)	2.85	3	3.15	V
		2.5 V (for 3 V I/O only)	2.375	2.5	2.625	V
		1.8 V	1.71	1.8	1.89	V
		1.5 V	1.425	1.5	1.575	V
		1.2 V	1.14	1.2	1.26	V
V_{CCIO_UIB}	Power supply for the Universal Interface Bus between the core and embedded HBM2 memory	1.2 V	1.17	1.2	1.23	V
V_{CCM_WORD}	Power supply for the embedded HBM2 memory	—	2.4	2.5	2.6	V
V_{CCA_PLL}	PLL analog voltage regulator power supply	—	1.71	1.8	1.89	V
V_I ¹¹ ¹²	DC input voltage	3 V I/O	–0.3	—	3.8	V
V_I ¹¹ ¹²	DC input voltage	LVDS I/O	–0.3	—	2.19	V
V_O	Output voltage	—	0	—	V_CCIO	V
T_J	Operating junction temperature for Intel^® Stratix^® 10 MX devices	Extended	0 ¹³	—	100 ¹⁴	°C
	Operating junction temperature for all other Intel^® Stratix^® 10 devices	Extended	0	—	100	°C
		Industrial	-20 (–40) ¹⁵	—	100	°C
t_RAMP ¹⁶ ¹⁷ ¹⁸ ¹⁹	Power supply ramp time	Standard POR	200 μs	—	100 ms	—

⁸ This value describes the required voltage measured between the PCB power and ground ball during normal device operation. The voltage ripple includes both regulator DC ripple and the dynamic noise. Refer to power distribution network (PDN) tool for PCB power distribution network design.

⁹ The use of Power Management Bus (PMBus™) voltage regulator dedicated to Intel^® Stratix^® 10 SmartVID devices is mandatory. The PMBus™ voltage regulator and Intel^® Stratix^® 10 SmartVID devices are connected via PMBus™.

¹⁰ You need to always power up V_CCBAT. If you do not use the design security feature in Intel^® Stratix^® 10 devices, connect V_CCBAT to a 1.8 V power supply. Intel^® Stratix^® 10 power-on reset (POR) circuitry monitors V_CCBAT.

¹¹ The LVDS I/O values are applicable to all dedicated and dual-function configuration I/Os.

¹² This value applies to both input and tri-stated output configuration. Pin voltage should not be externally pulled higher than the maximum value.

¹³ For use cases that require FPGA configuration at temperatures less than 0°C, contact Intel Premier Support to enable non-cold start applications.

¹⁴ Recommended maximum operating temperature for HBM2 is 95°C.

¹⁵ E-tile supports an operating temperature range of -40°C to 100°C. However, the E-tile transceivers may experience a higher error rate from -40°C to -20°C because of the calibration procedure when starting at a low temperature. Therefore, the recommended operating temperature range for E-tile protocol-compliant transceiver links is -20°C to 100°C. Additionally, for best results, extensive debug should be performed at 25°C or above.

¹⁶ This is also applicable to HPS power supply. For HPS power supply, refer to t_RAMP specifications for standard POR when HPS_PORSEL = 0 and t_RAMP specifications for fast POR when HPS_PORSEL = 1.

¹⁷ t_RAMP is the ramp time of each individual power supply, not the ramp time of all combined power supplies.

¹⁸ To support AS fast mode, all power supplies to the Intel^® Stratix^® 10 device must be fully ramped-up within 10 ms to the recommended operating conditions.

¹⁹ To support AS normal mode, V_{CCIO_SDM} of the Intel^® Stratix^® 10 device must be fully ramped-up within 10 ms to the recommended operating condition.

Transceiver Power Supply Operating Conditions

Table 7. Transceiver Power Supply Operating Conditions for Intel^® Stratix^® 10 GX/SX L-Tile Devices in a Non-Bonded Configuration
Symbol	Description	Datarate	Minimum	Typical	Maximum	Unit
V_{CCT_GXB[L,R]} and V_{CCR_GXB[L,R]}	Chip-to-chip ²⁰	1.0 Gbps to 26.6 Gbps ²¹ ²²	1.1	1.12	1.14	V
	Chip-to-chip ²⁰	1.0 Gbps to 17.4 Gbps ²¹ ²²	1.0	1.03 ²³	1.06	V
	Backplane ²⁴	1.0 Gbps to 12.5 Gbps ²¹	1.0	1.03 ²⁵, ²³	1.06	V
V_{CCH_GXB[L,R]}	Transceiver high voltage power	—	1.71 ²⁶	1.8	1.89	V

Table 8. Transceiver Power Supply Operating Conditions for Intel^® Stratix^® 10 GX/SX L-Tile Devices in a Bonded Configuration
Symbol	Description	Datarate	Minimum	Typical	Maximum	Unit
V_{CCT_GXB[L,R]} and V_{CCR_GXB[L,R]}	Chip-to-chip ²⁰	1.0 Gbps to 16.0 Gbps ²¹	1.0	1.03 ²³	1.06	V
	Chip-to-chip ²⁰	> 16.0 Gbps to 17.4 Gbps ²¹ ²²	1.1	1.12	1.14	V
	Backplane ²⁴	1.0 Gbps to 12.5 Gbps ²¹	1.0	1.03 ²⁵, ²³	1.06	V
V_{CCH_GXB[L,R]}	Transceiver high voltage power	—	1.71 ²⁶	1.8	1.89	V

Table 9. Transceiver Power Supply Operating Conditions for Intel^® Stratix^® 10 GX/SX/MX/TX H-Tile Devices in a Non-Bonded Configuration
Symbol	Description	Datarate	Minimum	Typical	Maximum	Unit
V_{CCT_GXB[L,R]} and V_{CCR_GXB[L,R]}	Chip-to-chip ²⁰and Backplane ²⁴	1.0 Gbps to 28.3 Gbps (GXT) ²¹	1.1	1.12	1.14	V
V_{CCT_GXB[L,R]} and V_{CCR_GXB[L,R]}	Chip-to-chip ²⁰and Backplane ²⁴	1.0 Gbps to 17.4 Gbps (GX) ²¹	1.0	1.03 ²³	1.06	V
V_{CCH_GXB[L,R]}	Transceiver high voltage power	—	1.71 ²⁶	1.8	1.89	V

Table 10. Transceiver Power Supply Operating Conditions for Intel^® Stratix^® 10 GX/SX/MX/TX H-Tile Devices in a Bonded Configuration
Symbol	Description	Datarate	Minimum	Typical	Maximum	Unit
V_{CCT_GXB[L,R]} and V_{CCR_GXB[L,R]}	Chip-to-chip ²⁰ and Backplane ²⁴	1.0 Gbps to 16.0 Gbps ²¹	1.0	1.03 ²³	1.06	V
V_{CCT_GXB[L,R]} and V_{CCR_GXB[L,R]}	Chip-to-chip ²⁰ and Backplane ²⁴	> 16.0 Gbps to 17.4 Gbps ²¹	1.1	1.12	1.14	V
V_{CCH_GXB[L,R]}	Transceiver high voltage power	—	1.71 ²⁶	1.8	1.89	V

Note: Most VCCR_GXB and VCCT_GXB pins associated with unused transceiver channels can be grounded on a per-tile basis to minimize power consumption. Refer to the Intel^® Stratix^® 10 Device Family Pin Connection Guidelines and the Intel^® Quartus^® Prime pin report for information about pinning out the package to minimize power consumption for your specific design.

Table 11. Transceiver Power Supply Operating Conditions for Intel^® Stratix^® 10 TX/MX E-Tile Devices
Symbol	Description	Minimum ²⁷	Typical	Maximum ²⁷	Unit	Noise Mask (at ball grid array (BGA))
V_{CCRT_GXE} ²⁸	Transceiver power supply	0.87	0.9	0.93	V	20 mVpp (100 kHz to 400 kHz) 3 mVpp (3 MHz to 500 MHz) 10 mVpp at 1 GHz
V_{CCRTPLL_GXE} ²⁸	Transceiver PLL power supply	0.87	0.9	0.93	V	6 mVpp at 100 kHz 1 mVpp (600 kHz to 10 MHz) 10 mVpp at 1 GHz
V_{CCH_GXE}	Analog power supply	1.067	1.1	1.133	V	10 mVpp (800 kHz to 500 MHz
V_{CCCLK_GXE}	LVPECL REFCLK power supply	2.375	2.5	2.625	V	—

²⁰ Chip-to-chip refers to transceiver links that are short reach and do not require advanced equalization such as decision feedback equalization (DFE).

²¹ Stratix 10 transceivers can support data rates below 1.0 Gbps through over sampling.

²² Bonded channels operating at datarates above 16.0 Gbps require 1.12 V ±20 mV at the pin. For channels that are placed on the same tile as the channels that require 1.12 V ±20 mV, V_{CCR_GXB} and V_{CCT_GXB} = 1.12 V ±20 mV.

²³ For a 1.03-V typical voltage, the maximum/minimum should be ± 30 mV; hence, V_MAX = 1.06 V. However, when these channels share the power supply with channels requiring a 1.12-V typical voltage, these channels should increase typical voltage to 1.12 V, with a maximum/minimum ± 20 mV; hence V_MAX = 1.14 V.

²⁴ Backplane applications refer to ones which require advanced equalization, such as DFE enabled, to compensate for channel loss.

²⁵ Refer to the Intel^® Quartus^® Prime Pro Edition software for the typical nominal value.

²⁶ In an optical transfer network (OTN) application, the minimum VCCH voltage specification at the package pin is 1.77 V.

²⁷ This value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance requirements. Refer to the PDN tool for the additional budget for the dynamic tolerance requirements.

²⁸ The difference between V_CCRT/V_CCRTPLL and V_CCH should be no less than 200 mV.

HPS Power Supply Operating Conditions

Table 12. HPS Power Supply Operating Conditions for Intel^® Stratix^® 10 DevicesThis table lists the steady-state voltage and current values expected for Intel^® Stratix^® 10 system-on-a-chip (SoC) devices with ARM^®-based hard processor system (HPS). Power supply ramps must all be strictly monotonic, without plateaus. Refer to Recommended Operating Conditions for Intel^® Stratix^® 10 Devices table for the steady-state voltage values expected from the FPGA portion of the Intel^® Stratix^® 10 SoC devices.
Symbol	Description	Condition	Minimum	Typical	Maximum	Unit
V_{CCL_HPS}	HPS core voltage and periphery circuitry power supply	–E2L, –I2L, –E3X, –I3X	0.87	0.9	0.93	V
		–E2L, –I2L, –E3X, –I3X	0.91	0.94	0.97	V
		–E1V, –I1V, –E2V, –I2V, –E3V, –I3V ²⁹	0.77 – 0.91	0.8 – 0.94	0.83 – 0.97	V
V_{CCPLLDIG_HPS}	HPS PLL digital power supply	–E2L, –I2L, –E3X, –I3X	0.87	0.9	0.93	V
		–E2L, –I2L, –E3X, –I3X	0.91	0.94	0.97	V
		–E1V, –I1V, –E2V, –I2V, –E3V, –I3V ²⁹	0.77 – 0.91	0.8 – 0.94	0.83 – 0.97	V
V_{CCPLL_HPS}	HPS PLL analog power supply	1.8 V	1.71	1.8	1.89	V
V_{CCIO_HPS}	HPS I/O buffers power supply	1.8 V	1.71	1.8	1.89	V

²⁹ The use of Power Management Bus (PMBus™) voltage regulator dedicated to Intel^® Stratix^® 10 SmartVID devices is mandatory. The PMBus™ voltage regulator and Intel^® Stratix^® 10 SmartVID devices are connected via PMBus™.

DC Characteristics

Supply Current and Power Consumption

Intel offers two ways to estimate power for your design—the Excel-based Early Power Estimator (EPE) and the Intel^® Quartus^® Prime Power Analyzer feature.

Use the Excel-based EPE before you start your design to estimate the supply current for your design. The EPE provides a magnitude estimate of the device power because these currents vary greatly with the usage of the resources.

The Intel^® Quartus^® Prime Power Analyzer provides better quality estimates based on the specifics of the design after you complete place-and-route. The Power Analyzer can apply a combination of user-entered, simulation-derived, and estimated signal activities that, when combined with detailed circuit models, yield very accurate power estimates.

I/O Pin Leakage Current

Table 13. I/O Pin Leakage Current for Intel^® Stratix^® 10 Devices
Symbol	Description	Condition	Min	Max	Unit
I_I	Input pin	V_I = 0 V to V_CCIOMAX	–80	80	µA
I_OZ	Tri-stated I/O pin	V_O = 0 V to V_CCIOMAX	–80	80	µA

Bus Hold Specifications

The bus-hold trip points are based on calculated input voltages from the JEDEC standard.

Table 14. Bus Hold Parameters for Intel^® Stratix^® 10 Devices
Parameter	Symbol	Condition	V_CCIO (V)										Unit
			1.2		1.5		1.8		2.5		3.0
			Min	Max	Min	Max	Min	Max	Min	Max	Min	Max
Bus-hold, low, sustaining current	I_SUSL	V_IN > V_IL (max)	8	—	12	—	30	—	60	—	70	—	µA
Bus-hold, high, sustaining current	I_SUSH	V_IN < V_IH (min)	–8	—	–12	—	–30	—	–60	—	–70	—	µA
Bus-hold, low, overdrive current	I_ODL	0 V < V_IN < V_CCIO	—	125	—	175	—	200	—	300	—	500	µA
Bus-hold, high, overdrive current	I_ODH	0 V < V_IN < V_CCIO	—	–125	—	–175	—	–200	—	–300	—	–500	µA
Bus-hold trip point	V_TRIP	—	0.3	0.9	0.38	1.13	0.68	1.07	0.7	1.7	0.8	2	V

OCT Calibration Accuracy Specifications

If you enable on-chip termination (OCT) calibration, calibration is automatically performed at power up for I/Os connected to the calibration block.

Table 15. OCT Calibration Accuracy Specifications for Intel^® Stratix^® 10 DevicesCalibration accuracy for the calibrated on-chip series termination (R_S OCT) and on-chip parallel termination (R_T OCT) are applicable at the moment of calibration. When process, voltage, and temperature (PVT) conditions change after calibration, the tolerance may change.
Symbol	Description	Condition (V)	Calibration Accuracy			Unit
Symbol	Description	Condition (V)	–E1, –I1	–E2, –I2	–E3, –I3	Unit
34-Ω, 48-Ω, 60-Ω, 80-Ω, 120-Ω, and 240-Ω R_S	Internal series termination with calibration (34-Ω, 48-Ω, 60-Ω, 80-Ω, 120-Ω, and 240-Ω setting)	V_CCIO = 1.2	±15	±15	±15	%
34-Ω and 40-Ω R_S	Internal series termination with calibration (34-Ω and 40-Ω setting)	V_CCIO = 1.5, 1.35, 1.25, 1.2	±15	±15	±15	%
25-Ω and 50-Ω R_S	Internal series termination with calibration (25-Ω and 50-Ω setting)	V_CCIO = 1.8, 1.5, 1.2	±15	±15	±15	%
34-Ω, 40-Ω, 48-Ω, 60-Ω, 80-Ω, 120-Ω, and 240-Ω R_T	Internal parallel termination with calibration (34-Ω, 40-Ω, 48-Ω, 60-Ω, 80-Ω, 120-Ω, and 240-Ω setting)	POD12 I/O standard, V_CCIO = 1.2	±15	±15	±15	%
48-Ω, 50-Ω, 60-Ω, and 120-Ω R_T	Internal parallel termination with calibration (48-Ω, 50-Ω, 60-Ω, and 120-Ω setting)	V_CCIO = 1.5, 1.2	–10 to +60	–10 to +60	–10 to +60	%
48-Ω, 60-Ω, and 120-Ω R_T	Internal parallel termination with calibration (48-Ω, 60-Ω, and 120-Ω setting)	V_CCIO = 1.25	–10 to +70	–10 to +70	–10 to +70	%
48-Ω, 60-Ω, and 120-Ω R_T	Internal parallel termination with calibration (48-Ω, 60-Ω, and 120-Ω setting)	V_CCIO = 1.35	–10 to +65	–10 to +65	–10 to +65	%
50-Ω R_T	Internal parallel termination with calibration (50-Ω setting)	V_CCIO = 1.8	–10 to +50	–10 to +50	–10 to +50	%

OCT Without Calibration Resistance Tolerance Specifications

Table 16. OCT Without Calibration Resistance Tolerance Specifications for Intel^® Stratix^® 10 DevicesThis table lists the Intel^® Stratix^® 10 OCT without calibration resistance tolerance to PVT changes.
Symbol	Description	I/O Buffer Type	Condition (V)	Resistance Tolerance			Unit
Symbol	Description	I/O Buffer Type	Condition (V)	–E1, –I1	–E2, –I2	–E3, –I3	Unit
25-Ω and 50-Ω R_S	Internal series termination without calibration (25-Ω and 50-Ω setting)	3 V I/O	V_CCIO = 3.0, 2.5, 1.8, 1.5, 1.2	–40 to +30	±40	±40	%
25-Ω and 50-Ω R_S	Internal series termination without calibration (25-Ω and 50-Ω setting)	LVDS I/O	V_CCIO = 1.8, 1.5, 1.2	–20 to +35	–20 to +35	–20 to +35	%
34-Ω and 40-Ω R_S	Internal series termination without calibration (34-Ω and 40-Ω setting)	LVDS I/O	V_CCIO = 1.5, 1.35, 1.25, 1.2	–20 to +35	–20 to +35	–20 to +35	%
48-Ω, 60-Ω, 80-Ω, and 240-Ω R_S	Internal series termination without calibration (48-Ω, 60-Ω, 80-Ω, and 240-Ω setting)	LVDS I/O	V_CCIO = 1.2	–20 to +35	–20 to +35	–20 to +35	%
100-Ω R_D	Internal differential termination (100-Ω setting)	LVDS I/O	V_CCIO = 1.8	±25	±35	±40	%

Pin Capacitance

Table 17. Pin Capacitance for Intel^® Stratix^® 10 Devices
Symbol	Description	Maximum	Unit
C_{IO_COLUMN}	Input capacitance on column I/O pins	3.5	pF
C_OUTFB	Input capacitance on dual-purpose clock output/feedback pins	3.5	pF

Internal Weak Pull-Up Resistor

All I/O pins, except configuration, test, and JTAG pins, have an option to enable weak pull-up. For SDM and HPS, the configuration I/O and peripheral I/O are supported with weak pull-up and weak pull-down options.

Table 18. Internal Weak Pull-Up Resistor Values for Intel^® Stratix^® 10 Devices
Symbol	Description	Condition (V)	Nominal Value	Resistance Tolerance	Unit
R_PU	Value of the I/O pin pull-up resistor before and during configuration, as well as user mode if you have enabled the programmable pull-up resistor option.	V_CCIO = 3.0 ±5%	25	±25%	kΩ
		V_CCIO = 2.5 ±5%	25	±25%	kΩ
		V_CCIO = 1.8 ±5%	25	±25%	kΩ
		V_CCIO = 1.5 ±5%	25	±25%	kΩ
		V_CCIO = 1.35 ±5%	25	±25%	kΩ
		V_CCIO = 1.25 ±5%	25	±25%	kΩ
		V_CCIO = 1.2 ±5%	25	±25%	kΩ

I/O Standard Specifications

Tables in this section list the input voltage (V_IH and V_IL), output voltage (V_OH and V_OL), and current drive characteristics (I_OH and I_OL) for various I/O standards supported by Intel^® Stratix^® 10 devices.

For minimum voltage values, use the minimum V_CCIO values. For maximum voltage values, use the maximum V_CCIO values.

You must perform timing closure analysis to determine the maximum achievable frequency for general purpose I/O standards.

Single-Ended I/O Standards Specifications

Table 19. Single-Ended I/O Standards Specifications for Intel^® Stratix^® 10 Devices
I/O Standard	V_CCIO(V)			V_IL(V)		V_IH(V)		V_OL(V)	V_OH(V)	I_OL ³⁰ (mA)	I_OH ³⁰ (mA)
I/O Standard	Min	Typ	Max	Min	Max	Min	Max	Max	Min	I_OL ³⁰ (mA)	I_OH ³⁰ (mA)
3.0-V LVTTL	2.85	3	3.15	–0.3	0.8	1.7	3.6	0.4	2.4	2	–2
3.0-V LVCMOS	2.85	3	3.15	–0.3	0.8	1.7	3.6	0.2	V_CCIO – 0.2	0.1	–0.1
2.5 V	2.375	2.5	2.625	–0.3	0.7	1.7	3.3	0.4	2	1	–1
1.8 V	1.71	1.8	1.89	-0.3	0.35 × V_CCIO	0.65 × V_CCIO	V_CCIO + 0.3	0.45	V_CCIO – 0.45	2	–2
1.5 V	1.425	1.5	1.575	–0.3	0.35 × V_CCIO	0.65 × V_CCIO	V_CCIO + 0.3	0.25 × V_CCIO	0.75 × V_CCIO	2	–2
1.2 V	1.14	1.2	1.26	–0.3	0.35 × V_CCIO	0.65 × V_CCIO	V_CCIO + 0.3	0.25 × V_CCIO	0.75 × V_CCIO	2	–2
Schmitt Trigger Input	1.71	1.8	1.89	—	0.35 × V_CCIO	0.65 × V_CCIO	—	—	—	—	—

³⁰ To meet the I_OL and I_OH specifications, you must set the current strength settings accordingly. For example, to meet the 1.8- V LVCMOS specification (4 mA), you should set the current strength settings to 4 mA. Setting at lower current strength may not meet the I_OL and I_OH specifications in the datasheet.

Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications

Table 20. Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications for Intel^® Stratix^® 10 Devices
I/O Standard	V_CCIO (V)			V_REF (V)			V_TT (V)
I/O Standard	Min	Typ	Max	Min	Typ	Max	Min	Typ	Max
SSTL-18  Class I, II	1.71	1.8	1.89	0.833	0.9	0.969	V_REF - 0.04	V_REF	V_REF + 0.04
SSTL-15  Class I, II	1.425	1.5	1.575	0.49 × V_CCIO	0.5 × V_CCIO	0.51 × V_CCIO	0.49 × V_CCIO	0.5 × V_CCIO	0.51 × V_CCIO
SSTL-135	1.283	1.35	1.45	0.49 × V_CCIO	0.5 × V_CCIO	0.51 × V_CCIO	0.49 × V_CCIO	0.5 × V_CCIO	0.51 × V_CCIO
SSTL-125	1.19	1.25	1.31	0.49 × V_CCIO	0.5 × V_CCIO	0.51 × V_CCIO	0.49 × V_CCIO	0.5 × V_CCIO	0.51 × V_CCIO
SSTL-12	1.14	1.2	1.26	0.49 × V_CCIO	0.5 × V_CCIO	0.51 × V_CCIO	0.49 × V_CCIO	0.5 × V_CCIO	0.51 × V_CCIO
HSTL-18  Class I, II	1.71	1.8	1.89	0.85	0.9	0.95	—	V_CCIO/2	—
HSTL-15  Class I, II	1.425	1.5	1.575	0.68	0.75	0.9	—	V_CCIO/2	—
HSTL-12  Class I, II	1.14	1.2	1.26	0.47 × V_CCIO	0.5 × V_CCIO	0.53 × V_CCIO	—	V_CCIO/2	—
HSUL-12	1.14	1.2	1.3	0.49 × V_CCIO	0.5 × V_CCIO	0.51 × V_CCIO	—	—	—
POD12	1.14	1.2	1.26	—	Internally calibrated	—	—	V_CCIO	—

Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications

Table 21. Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications for Intel^® Stratix^® 10 Devices
I/O Standard	V_IL(DC)(V)		V_IH(DC) (V)		V_IL(AC) (V)	V_IH(AC) (V)	V_OL (V)	V_OH (V)	I_OL ³¹ (mA)	I_OH ³¹ (mA)
I/O Standard	Min	Max	Min	Max	Max	Min	Max	Min	I_OL ³¹ (mA)	I_OH ³¹ (mA)
SSTL-18 Class I	–0.3	V_REF –0.125	V_REF + 0.125	V_CCIO + 0.3	V_REF – 0.25	V_REF + 0.25	V_TT – 0.603	V_TT + 0.603	6.7	–6.7
SSTL-18 Class II	–0.3	V_REF –0.125	V_REF + 0.125	V_CCIO + 0.3	V_REF – 0.25	V_REF + 0.25	0.28	V_CCIO –0.28	13.4	–13.4
SSTL-15 Class I	—	V_REF – 0.1	V_REF + 0.1	—	V_REF – 0.175	V_REF + 0.175	0.2 × V_CCIO	0.8 × V_CCIO	8	–8
SSTL-15 Class II	—	V_REF – 0.1	V_REF + 0.1	—	V_REF – 0.175	V_REF + 0.175	0.2 × V_CCIO	0.8 × V_CCIO	16	–16
SSTL-135	—	V_REF – 0.09	V_REF + 0.09	—	V_REF – 0.16	V_REF + 0.16	0.2 × V_CCIO	0.8 × V_CCIO	—	—
SSTL-125	—	V_REF – 0.09	V_REF + 0.09	—	V_REF – 0.15	V_REF + 0.15	0.2 × V_CCIO	0.8 × V_CCIO	—	—
SSTL-12	—	V_REF – 0.10	V_REF + 0.10	—	V_REF – 0.15	V_REF + 0.15	0.2 × V_CCIO	0.8 × V_CCIO	—	—
HSTL-18 Class I	—	V_REF –0.1	V_REF + 0.1	—	V_REF – 0.2	V_REF + 0.2	0.4	V_CCIO – 0.4	8	–8
HSTL-18 Class II	—	V_REF – 0.1	V_REF + 0.1	—	V_REF – 0.2	V_REF + 0.2	0.4	V_CCIO – 0.4	16	–16
HSTL-15 Class I	—	V_REF – 0.1	V_REF + 0.1	—	V_REF – 0.2	V_REF + 0.2	0.4	V_CCIO – 0.4	8	–8
HSTL-15 Class II	—	V_REF – 0.1	V_REF + 0.1	—	V_REF – 0.2	V_REF + 0.2	0.4	V_CCIO –0.4	16	–16
HSTL-12 Class I	–0.15	V_REF – 0.08	V_REF + 0.08	V_CCIO + 0.15	V_REF – 0.15	V_REF+ 0.15	0.25 × V_CCIO	0.75 × V_CCIO	8	–8
HSTL-12 Class II	–0.15	V_REF – 0.08	V_REF + 0.08	V_CCIO + 0.15	V_REF – 0.15	V_REF+ 0.15	0.25 × V_CCIO	0.75 × V_CCIO	16	–16
HSUL-12	—	V_REF – 0.13	V_REF + 0.13	—	V_REF – 0.22	V_REF+ 0.22	0.1 × V_CCIO	0.9 × V_CCIO	—	—
POD12	–0.15	V_REF – 0.08	V_REF + 0.08	V_CCIO + 0.15	V_REF – 0.15	V_REF+ 0.15	—	—	—	—

³¹ To meet the I_OL and I_OH specifications, you must set the current strength settings accordingly. For example, to meet the SSTL15CI specification (8 mA), you should set the current strength settings to 8 mA. Setting at lower current strength may not meet the I_OL and I_OH specifications in the datasheet.

Differential SSTL I/O Standards Specifications

Table 22. Differential SSTL I/O Standards Specifications for Intel^® Stratix^® 10 Devices
I/O Standard	V_CCIO (V)			V_SWING(DC) (V)		V_SWING(AC) (V)		V_IX(AC) (V)
I/O Standard	Min	Typ	Max	Min	Max	Min	Max	Min	Typ	Max
SSTL-18 Class I, II	1.71	1.8	1.89	0.25	V_CCIO+ 0.6	0.5	V_CCIO + 0.6	V_CCIO/2 – 0.175	—	V_CCIO/2 + 0.175
SSTL-15 Class I, II	1.425	1.5	1.575	0.2	³²	2(V_IH(AC) – V_REF)	2(V_REF – V_IL(AC))	V_CCIO/2 – 0.15	—	V_CCIO/2 + 0.15
SSTL-135	1.283	1.35	1.45	0.18	³²	2(V_IH(AC) – V_REF)	2(V_IL(AC) – V_REF)	V_CCIO/2 – 0.15	—	V_CCIO/2 + 0.15
SSTL-125	1.19	1.25	1.31	0.18	³²	2(V_IH(AC) – V_REF)	2(V_IL(AC) – V_REF)	V_CCIO/2 – 0.15	—	V_CCIO/2 + 0.15
SSTL-12	1.14	1.2	1.26	0.16	³²	2(V_IH(AC) – V_REF)	2(V_IL(AC) – V_REF)	V_REF – 0.15	V_CCIO/2	V_REF + 0.15

³² The maximum value for V_SWING(DC) is not defined. However, each single-ended signal needs to be within the respective single-ended limits (V_IH(DC) and V_IL(DC)).

Differential HSTL and HSUL I/O Standards Specifications

Table 23. Differential HSTL and HSUL I/O Standards Specifications for Intel^® Stratix^® 10 Devices
I/O Standard	V_CCIO (V)			V_DIF(DC) (V)		V_DIF(AC) (V)		V_X(AC) (V)			V_CM(DC) (V)
I/O Standard	Min	Typ	Max	Min	Max	Min	Max	Min	Typ	Max	Min	Typ	Max
HSTL-18 Class I, II	1.71	1.8	1.89	0.2	—	0.4	—	0.78	—	1.12	0.78	—	1.12
HSTL-15 Class I, II	1.425	1.5	1.575	0.2	—	0.4	—	0.68	—	0.9	0.68	—	0.9
HSTL-12 Class I, II	1.14	1.2	1.26	0.16	V_CCIO+ 0.3	0.3	V_CCIO + 0.48	—	0.5 × V_CCIO	—	0.4 × V_CCIO	0.5 × V_CCIO	0.6 ×  V_CCIO
HSUL-12	1.14	1.2	1.3	2(V_IH(DC) – V_REF)	2(V_REF – V_IH(DC))	2(V_IH(AC) – V_REF)	2(V_REF – V_IH(AC))	0.5 × V_CCIO – 0.12	0.5 × V_CCIO	0.5 ×  V_CCIO +0.12	0.4 × V_CCIO	0.5 × V_CCIO	0.6 ×  V_CCIO

Differential I/O Standards Specifications

Table 24. Differential I/O Standards Specifications for Intel^® Stratix^® 10 Devices
I/O Standard	V_CCIO (V)			V_ID (mV) ³³		V_ICM(DC) (V)			V_OD (V) ³⁴ ³⁵			V_OCM (V) ³⁴
I/O Standard	Min	Typ	Max	Min	Max	Min	Condition	Max	Min	Typ	Max	Min	Typ	Max
LVDS ³⁶	1.71	1.8	1.89	100	—	0.05	Data rate ≤700 Mbps	1.65	0.247	—	0.6	1.125	1.25	1.375
LVDS ³⁶	1.71	1.8	1.89	100	—	1	Data rate >700 Mbps	1.6	0.247	—	0.6	1.125	1.25	1.375
RSDS ³⁷	1.71	1.8	1.89	100	—	0.3	—	1.4	0.1	0.2	0.6	0.5	1.2	1.4
Mini-LVDS ³⁸	1.71	1.8	1.89	200	600	0.4	—	1.325	0.25	—	0.6	1	1.2	1.4
LVPECL ³⁹	1.71	1.8	1.89	300	—	0.6	Data rate ≤700 Mbps	1.7	—	—	—	—	—	—
LVPECL ³⁹	1.71	1.8	1.89	300	—	1	Data rate >700 Mbps	1.6	—	—	—	—	—	—

³³ The minimum V_ID value is applicable over the entire common mode range, V_CM.

³⁴ R_L range: 90 ≤ R_L ≤ 110 Ω.

³⁵ The specification is only applicable to default V_OD setting.

³⁶ For optimized LVDS receiver performance, the receiver voltage input range must be within 1.0 V to 1.6 V for data rates above 700 Mbps and 0.05 V to 1.65 V for data rates below 700 Mbps.

³⁷ For optimized RSDS receiver performance, the receiver voltage input range must be within 0.3 V to 1.4 V.

³⁸ For optimized Mini-LVDS receiver performance, the receiver voltage input range must be within 0.4 V to 1.325 V.

³⁹ For optimized LVPECL receiver performance, the receiver voltage input range must be within 0.85 V to 1.75 V for data rates above 700 Mbps and 0.45 V to 1.95 V for data rates below 700 Mbps.

Switching Characteristics

This section provides the performance characteristics of Intel^® Stratix^® 10 core and periphery blocks.

Periphery Performance Specifications

This section describes the periphery performance, high-speed I/O, and external memory interface.

Actual achievable frequency depends on design and system specific factors. Ensure proper timing closure in your design and perform HSPICE/IBIS simulations based on your specific design and system setup to determine the maximum achievable frequency in your system.

High-Speed I/O Specifications

Table 25. High-Speed I/O Specifications for Intel^® Stratix^® 10 Devices
When serializer/deserializer (SERDES) factor J = 3 to 10, use the SERDES block.

For LVDS applications, you must use the PLLs in integer PLL mode.

You must calculate the leftover timing margin in the receiver by performing link timing closure analysis. You must consider the board skew margin, transmitter channel-to-channel skew, and receiver sampling margin to determine the leftover timing margin.
Symbol		Condition	–E1V, –I1V			–E2V, –E2L, –I2L, –I2V			–E3V, –E3X, –I3X, –I3V			Unit
Symbol		Condition	Min	Typ	Max	Min	Typ	Max	Min	Typ	Max	Unit
f_{HSCLK_in}(input clock frequency) True Differential I/O Standards		Clock boost factor  W = 1 to 40 ⁴⁰	10	—	800	10	—	700	10	—	625	MHz
f_{HSCLK_in}(input clock frequency) Single-Ended I/O Standards		Clock boost factor  W = 1 to 40 ⁴⁰	10	—	625	10	—	625	10	—	525	MHz
f_{HSCLK_OUT} (output clock frequency)		—	—	—	800 ⁴¹	—	—	700 ⁴¹	—	—	625 ⁴¹	MHz
Transmitter	True Differential I/O Standards - f_HSDR (data rate) ⁴²	SERDES factor J = 4 to 10 ⁴³ ⁴⁵ ⁴⁴	⁴⁵	—	1600	⁴⁵	—	1434	⁴⁵	—	1250	Mbps
		SERDES factor J = 3 ⁴³ ⁴⁵ ⁴⁴	⁴⁵	—	1,000	⁴⁵	—	1,000	⁴⁵	—	938	Mbps
		SERDES factor J = 2, uses DDR registers	⁴⁵	—	840 ⁴⁶	⁴⁵	—	⁴⁶	⁴⁵	—	⁴⁶	Mbps
		SERDES factor J = 1, uses DDR registers	⁴⁵	—	420 ⁴⁶	⁴⁵	—	⁴⁶	⁴⁵	—	⁴⁶	Mbps
	t_{x Jitter}- True Differential I/O Standards	Total jitter for data rate, 600 Mbps – 1.6 Gbps	—	—	160	—	—	200	—	—	250	ps
	t_{x Jitter}- True Differential I/O Standards	Total jitter for data rate, < 600 Mbps	—	—	0.1	—	—	0.12	—	—	0.15	UI
	t_DUTY ⁴⁷	TX output clock duty cycle for Differential I/O Standards	45	50	55	45	50	55	45	50	55	%
	t_RISE & t_FALL ⁴⁴ ⁴⁸	True Differential I/O Standards	—	—	160	—	—	180	—	—	200	ps
	TCCS ⁴⁷ ⁴²	True Differential I/O Standards	—	—	330	—	—	330	—	—	330	ps
Receiver	True Differential I/O Standards - f_HSDRDPA (data rate)	SERDES factor J = 4 to 10 ⁴³ ⁴⁵ ⁴⁴	—	—	1600	—	—	1434	—	—	1250	Mbps
	True Differential I/O Standards - f_HSDRDPA (data rate)	SERDES factor J = 3 ⁴³ ⁴⁵ ⁴⁴	—	—	1,000	—	—	1,000	—	—	938	Mbps
	f_HSDR (data rate) (without DPA) ⁴²	SERDES factor J = 3 to 10	⁴⁵	—	⁴⁹	⁴⁵	—	⁴⁹	⁴⁵	—	⁴⁹	Mbps
		SERDES factor J = 2, uses DDR registers	⁴⁵	—	⁴⁶	⁴⁵	—	⁴⁶	⁴⁵	—	⁴⁶	Mbps
		SERDES factor J = 1, uses DDR registers	⁴⁵	—	⁴⁶	⁴⁵	—	⁴⁶	⁴⁵	—	⁴⁶	Mbps
DPA (FIFO mode)	DPA run length	—	—	—	10000	—	—	10000	—	—	10000	UI
DPA (soft CDR mode)	DPA run length	SGMII/GbE protocol	—	—	5	—	—	5	—	—	5	UI
DPA (soft CDR mode)	DPA run length	All other protocols	—	—	50 data transition per 208 UI	—	—	50 data transition per 208 UI	—	—	50 data transition per 208 UI	—
Soft CDR mode	Soft-CDR ppm tolerance	—	–300	—	300	–300	—	300	–300	—	300	ppm
Non DPA mode	Sampling Window	—	—	—	330	—	—	330	—	—	330	ps

⁴⁰ Clock Boost Factor (W) is the ratio between the input data rate and the input clock rate.

⁴¹ This is achieved by using the PHY clock network.

⁴² Requires package skew compensation with PCB trace length.

⁴³ The F_max specification is based on the fast clock used for serial data. The interface F_max is also dependent on the parallel clock domain which is design dependent and requires timing analysis.

⁴⁴ The V_CC and V_CCP must be on a combined power layer and a maximum load of 5 pF for chip-to-chip interface.

⁴⁵ The minimum specification depends on the clock source (for example, the PLL and clock pin) and the clock routing resource (global, regional, or local) that you use. The I/O differential buffer and serializer do not have a minimum toggle rate.

⁴⁶ The maximum ideal data rate is the SERDES factor (J) x the PLL maximum output frequency (f_OUT) provided you can close the design timing and the signal integrity meets the interface requirements.

⁴⁷ Not applicable for DIVCLK = 1.

⁴⁸ This applies to default pre-emphasis and V_OD settings only.

⁴⁹ You can estimate the achievable maximum data rate for non-DPA mode by performing link timing closure analysis. You must consider the board skew margin, transmitter delay margin, and receiver sampling margin to determine the maximum data rate supported.

DPA Lock Time Specifications

Figure 2. DPA Lock Time Specifications with DPA PLL Calibration Enabled

Table 26. DPA Lock Time Specifications for Intel^® Stratix^® 10 DevicesThe specifications are applicable to both commercial and industrial grades. The DPA lock time is for one channel. One data transition is defined as a 0-to-1 or 1-to-0 transition.
Standard	Training Pattern	Number of Data Transitions in One Repetition of the Training Pattern	Number of Repetitions per 256 Data Transitions ⁵⁰	Maximum Data Transition
SPI-4	00000000001111111111	2	128	640
Parallel Rapid I/O	00001111	2	128	640
Parallel Rapid I/O	10010000	4	64	640
Miscellaneous	10101010	8	32	640
Miscellaneous	01010101	8	32	640

⁵⁰ This is the number of repetitions for the stated training pattern to achieve the 256 data transitions.

LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specifications

Figure 3. LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specifications for a Data Rate Equal to 1.6 Gbps

Table 27. LVDS Soft-CDR/DPA Sinusoidal Jitter Mask Values for a Data Rate Equal to 1.6 Gbps
Jitter Frequency (Hz)		Sinusoidal Jitter (UI)
F1	10,000	25.00
F2	17,565	25.00
F3	1,493,000	0.28
F4	50,000,000	0.28

Figure 4. LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specifications for a Data Rate Less than 1.6 Gbps

Memory Standards Supported by the Hard Memory Controller

Table 28. Memory Standards Supported by the Hard Memory Controller for Intel^® Stratix^® 10 DevicesThis table lists the overall capability of the hard memory controller. For specific details, refer to the External Memory Interface Spec Estimator.
Memory Standard	Rate Support	Ping Pong PHY Support	Maximum Frequency (MHz)
DDR4 SDRAM	Quarter rate	Yes	1,333
DDR3 SDRAM	Quarter rate ⁵¹	Yes	1,066
DDR3L SDRAM	Quarter rate	Yes	1,066

⁵¹ Half rate support is only up to 667 MHz.

Memory Standards Supported by the Soft Memory Controller

Table 29. Memory Standards Supported by the Soft Memory Controller for Intel^® Stratix^® 10 DevicesThis table lists the overall capability of the soft memory controller. For specific details, refer to the External Memory Interface Spec Estimator.
Memory Standard	Rate Support	Maximum Frequency (MHz)
RLDRAM 3 ⁵²	Quarter rate	1,200
QDR IV SRAM	Quarter rate	1,066
QDR II SRAM	Half rate ⁵³	350
QDR II+ SRAM	Half rate	550
QDR II+ Xtreme SRAM	Half rate	633

⁵² For Intel^® Stratix^® 10 RLDRAM 3, Intel only provides the PHY-only option.

⁵³ Full rate support is only up to 334 MHz.

Memory Standards Supported by the HPS Hard Memory Controller

Table 30. Memory Standards Supported by the HPS Hard Memory Controller for Intel^® Stratix^® 10 DevicesThis table lists the overall capability of the hard memory controller. For specific details, refer to the External Memory Interface Spec Estimator.
Memory Standard	Rate Support	Maximum Frequency (MHz)
DDR4 SDRAM	Half rate	1,066
DDR3 SDRAM	Half rate	1,066
DDR3L SDRAM	Half rate	1,066

Performance Specifications of the HBM2 Interface in Intel Stratix 10 MX Devices

Table 31. Performance Specifications of the HBM2 Interface in Intel^® Stratix^® 10 MX Devices
Intel^® Stratix^® 10 MX Device Speed Grade	Maximum HBM2 Interface Frequency (MHz)
-1	1000
-2	800
-3	600

HBM2 Interface Performance

Figure 5. HBM2 Performance in a 4GB4H HBM2 Device (64B access)

Figure 6. HBM2 Performance in a 8GB8H HBM2 Device (64B access)

Note:

These graphs show the Efficiency information for the HBM2 interface running at 800 MHz in an Intel^® Stratix^® 10 MX device with -2 Speed Grade using 64B access, with the re-order buffer turned off and different AXI Transaction IDs enabled. Contact Factory to get the Efficiency information for other Access Configurations.
Final timing closure available in Intel^® Quartus^® Prime 19.1.

DLL Range Specifications

Table 32. DLL Frequency Range Specifications for Intel^® Stratix^® 10 Devices
Parameter	Performance (for All Speed Grades)	Unit
DLL operating frequency range	600 – 1,333 ⁵⁴	MHz
DLL reference clock input	Minimum 600	MHz

⁵⁴ In the SX device family, if the HPS EMIF is instantiated, the maximum speed for that instantiation is 1,066 MHz.

Memory Output Clock Jitter Specifications

The clock jitter specification applies to the memory output clock pins clocked by an I/O PLL, or generated using differential signal-splitter and double data I/O circuits clocked by a PLL output routed on a PHY clock network as specified. Intel recommends using PHY clock networks for better jitter performance.

The memory clock output jitter is within the JEDEC specifications with an input of 10 ps peak-to-peak jitter.

OCT Calibration Block Specifications

Table 33. OCT Calibration Block Specifications for Intel^® Stratix^® 10 Devices
Symbol	Description	Min	Typ	Max	Unit
OCTUSRCLK	Clock required by OCT calibration blocks	—	—	20	MHz
T_OCTCAL	Number of OCTUSRCLK clock cycles required for R_SOCT /R_T OCT calibration	> 2000	—	—	Cycles
T_OCTSHIFT	Number of OCTUSRCLK clock cycles required for OCT code to shift out	—	32	—	Cycles
T_{RS_RT}	Time required between the `dyn_term_ctrl` and `oe` signal transitions in a bidirectional I/O buffer to dynamically switch between R_S OCT and R_TOCT	—	8	—	Full-rate cycle

Figure 7. Timing Diagram for on oe and dyn_term_ctrl Signals

L-Tile Transceiver Performance Specifications

Transceiver Performance for Intel Stratix 10 GX/SX L-Tile Devices

Table 34. Intel^® Stratix^® 10 GX/SX L-Tile Transmitter and Receiver Datarate Performance
Symbol/Description	Transceiver Speed Grade
Symbol/Description	-1	-2	-3
Chip-to-chip	N/A	26.6 Gbps 8 channels per tile ⁵⁵	17.4 Gbps
Backplane	N/A	12.5 Gbps	12.5 Gbps

Note: Refer to the Transceiver Power Supply Operating Conditions for V_{CCR_GXB} and V_{CCT_GXB} specifications when using bonded and non-bonded transceiver channels in Intel^® Stratix^® 10 L-Tile devices.

Table 35. L-Tile ATX PLL Performance
Symbol/Description	Condition	Transceiver Speed Grade 2	Transceiver Speed Grade 3	Unit
Supported Output Frequency	Maximum Frequency	13.3	8.7	GHz
Supported Output Frequency	Minimum Frequency	500		MHz
t_LOCK ⁵⁶	Maximum Frequency	1		ms
t_ARESET Required Reset Time ⁵⁷ ⁵⁸	—	25		Avalon Clock Cycles

Note: TX jitter specifications for the SerialLite III protocol at 17.4 Gbps are as low as: TJ = 0.32 UI, RJ = 0.15 UI, DJ = 0.18 UI, and DCD = 0.05 UI.

Table 36. L-Tile fPLL Performance
Symbol/Description	Condition	Mode	All Transceiver Speed Grades	Unit
Supported Output Frequency (VCO frequency based)	Maximum datarate	Transceiver - HDMI	12.5	Gbps
		Transceiver - General	12.5
		Transceiver - OTN, SDI Cascade	14.025
	Minimum datarate	Transceiver - HDMI	4.6	Gbps
		Transceiver - General	6
		Transceiver - OTN, SDI Cascade	7
t_LOCK ⁵⁶	Maximum Frequency		1	ms
t_ARESET Required Reset Time ⁵⁷ ⁵⁸	—		25	Avalon Clock Cycles

Table 37. L-Tile CMU PLL Performance
Symbol/Description	Condition	All Transceiver Speed Grades	Unit
Supported Output Frequency (VCO frequency based)	Maximum Frequency	5.15625	GHz
Supported Output Frequency (VCO frequency based)	Minimum Frequency	2.3	GHz
t_LOCK ⁵⁶	Maximum Frequency	1	ms
t_ARESET Required Reset Time ⁵⁷ ⁵⁸	—	25	Avalon Clock Cycles

⁵⁵ Refer to AN-778: Intel^® Stratix^® 10 Transceiver Usage for more details on channel selection requirements.

⁵⁶ This specification applies after the ATX PLL, fPLL, or CMU PLL has completed calibration.

⁵⁷ You must use the Avalon-MM interface to hold the PLLs in reset for the specified cycles by writing to the ATX PLL, fPLL, or CMU PLL pll_powerdown register.

⁵⁸ You must assert pll_powerdown for a minimum of 25 cycles are required if you are using a 250-MHz AVMM clock.

Transceiver Specifications for Intel Stratix 10 GX/SX L-Tile Devices

Table 38. L-Tile Reference Clock Specifications
Symbol/Description	Condition	All Transceiver Speed Grades			Unit
Symbol/Description	Condition	Min	Typ	Max	Unit
Supported I/O Standards	Dedicated reference clock pin	CML, Differential LVPECL, LVDS, and HCSL
Supported I/O Standards	RX reference clock pin	CML, Differential LVPECL, and LVDS
Input Reference Clock Frequency (CMU PLL)		50	—	800	MHz
Input Reference Clock Frequency (ATX PLL)		100	—	800	MHz
Input Reference Clock Frequency (fPLL)		50 ⁵⁹	—	800	MHz
Rise time	20% to 80%	—	—	350	ps
Fall time	80% to 20%	—	—	350	ps
Duty cycle	—	45	—	55	%
Spread-spectrum modulating clock frequency	PCIe	30	—	33	kHz
Spread-spectrum downspread	PCIe	—	0 to –0.5	—	%
On-chip termination resistors	—	—	100	—	Ω
Absolute V_MAX	Dedicated reference clock pin	—	—	1.6	V
Absolute V_MAX	RX reference clock pin	—	—	1.2	V
Absolute V_MIN	—	–0.4	—	—	V
Peak-to-peak differential input voltage	—	200	—	1600	mV
V_ICM (AC coupled)	V_{CCR_GXB} =1.03 V	—	0	—	V
V_ICM (DC coupled)	HCSL I/O standard for PCIe reference clock	250	—	550	mV
Transmitter `REFCLK` Phase Noise (800 MHz) ⁶⁰	100 Hz	—	—	–70	dBc/Hz
	1 kHz	—	—	–90	dBc/Hz
	10 kHz	—	—	–100	dBc/Hz
	100 kHz	—	—	–110	dBc/Hz
	≥ 1 MHz	—	—	–120	dBc/Hz
R_REF	—	2.0 k ±1%	—	2.0 k ±1%	Ω
T_{SSC-MAX-PERIOD-SLEW}	Max spread spectrum clocking (SSC) df/dt			0.75

Note: When using PCI Express, you must meet the reference clock phase jitter requirements as specified in the 4.3.7 Refclk Specifications for 2.5 GT/s and 5.0 GT/s and 4.3.8 Refclk Specification for 8.0 GT/s sections of the PCI Express Base Specification Revision 3.0.

Table 39. L-Tile Transceiver Clock Network Maximum Data Rate Specifications
Clock Network	Maximum Performance ⁶¹			Channel Span	Unit
Clock Network	ATX	fPLL	CMU	Channel Span	Unit
x1	17.4	12.5	10.3125	6 channels	Gbps
x6	17.4	12.5	N/A	6 channels	Gbps
x24	17.4 ⁶⁵	12.5	N/A	2 banks up and 1 bank down (total 24 channels) or 2 banks down and 1 bank up (total 24 channels)	Gbps
GXT clock lines	26.6	N/A	N/A	4 GXT channels within the same transceiver bank and 2 from the bank above or 2 from the bank below. ⁶²	Gbps

Table 40. L-Tile Receiver Specifications
Symbol/Description	Condition	Transceiver Speed Grade 3			Unit
Symbol/Description	Condition	Min	Typ	Max	Unit
Supported I/O Standards	—	High Speed Differential I/O, CML, Differential LVPECL, and LVDS
Absolute V_MAX for a receiver pin ⁶³	—	—	—	1.2	V
Absolute V_MIN for a receiver pin ⁶³ ⁶⁴	—	-0.4	—	—	V
Maximum peak-to-peak differential input voltage V_ID (diff p-p)	V_{CCR_GXB} = 1.03 V ⁶⁵	—	—	2.0	V
Differential on-chip termination resistors	85-Ω setting	—	85 ± 20%	—	Ω
Differential on-chip termination resistors	100-Ω setting	—	100 ± 20%	—	Ω
V_ICM (AC coupled)	V_{CCR_GXB} = 1.03 V	—	700	—	mV
V_ICM (AC coupled)	V_{CCR_GXB} = 1.12 V	—	750	—	mV
t_LTR ⁶⁶	—	—	—	1	ms
t_LTD ⁶⁷	—	4	—	—	µs
t_{LTD_manual} ⁶⁸	—	4	—	—	µs
t_{LTR_LTD_manual} ⁶⁹	—	15	—	—	µs
Run Length	—	—	—	200	UI
CDR ppm tolerance	PCIe-only	-300	—	300	ppm
CDR ppm tolerance	All other protocols	-1000	—	1000	ppm

Table 41. L-Tile Transmitter Specifications
Symbol/Description	Condition	Transceiver Speed Grade 2 and 3			Unit
Symbol/Description	Condition	Min	Typ	Max	Unit
Supported I/O Standards	—	High Speed Differential I/O ⁷⁰			—
Differential on-chip termination resistors	85-Ω setting	—	85 ± 20%	—	Ω
Differential on-chip termination resistors	100-Ω setting	—	100 ± 20%	—	Ω
V_OCM (AC coupled)	V_{CCT_GXB} = 1.03 V	—	515	—	mV
Rise time ⁷¹	20% to 80%	20	—	130	ps
Fall time ⁷¹	80% to 20%	20	—	130	ps
Intra-differential pair skew	TX V_CM = 0.5 V and slew rate of 15 ps	—	—	15 ⁷²	ps

Table 42. L-Tile Typical Transmitter V_OD Settings
Symbol	V_OD Setting ⁷³	V_OD/V_{CCT_GXB}Ratio
V_OD differential value = V_OD/V_{CCT_GXB} ratio x V_{CCT_GXB}	31	1.00
	30	0.97
	29	0.93
	28	0.90
	27	0.87
	26	0.83
	25	0.80
	24	0.77
	23	0.73
	22	0.70
	21	0.67
	20	0.63
	19	0.60
	18	0.57
	17	0.53
	16	0.50
	15	0.47
	14	0.43
	13	0.40
	12	0.37

Table 43. L-Tile Transmitter Channel-to-channel Skew Specifications
Mode	Channel Span	Maximum Skew	Unit
x6 Clock	Up to 6 channels in one bank	61	ps
x24 Clock	Up to 24 channels in one tile	500 ⁷⁴	ps

Table 44. Transceiver Clocks Specifications for Intel^® Stratix^® 10 L-Tile Devices
Clock	Value	Unit
`reconfig_clk`	≤ 150	MHz
`fixed_clk` for the RX detect circuit	250 ± 20%	MHz

For OSC_CLK_1 specifications, refer to the External Configuration Clock Source Requirements section.

⁵⁹ The f_MIN is 25 MHz when the fPLL is used for the HDMI protocol.

⁶⁰ To calculate the REFCLK phase noise requirement at frequencies other than 800 MHz, use the following formula: REFCLK phase noise at f (MHz) = REFCLK phase noise at 800 MHz + 20*log(f/800).

⁶¹ The maximum data rate depends on speed grade.

⁶² If the upper ATX PLL in a bank is used as the main GXT PLL, then the channel span includes two GXT channels from the bank above. If the lower ATX PLL in a bank is used as the main GXT PLL, then the channel span includes two GXT channels from the bank below.

⁶³ The device cannot tolerate prolonged operation at this absolute maximum.

⁶⁴ A passive pull up resistance prevents a 0-V common mode voltage on AC coupled receiver pins before the FPGA is configured.

⁶⁵ Bonded channels operating at data rates above 16 Gbps require 1.12 V ± 20 mV at the pin. For a given L-Tile, if there are channels that need the higher power supply, tie all the channels on that side to the higher power supply.

⁶⁶ t_LTR is the time required for the receiver CDR to lock to the input reference clock frequency after coming out of reset, or after the CDR's calibration is complete.

⁶⁷ t_LTD is time required for the receiver CDR to start recovering valid data after the rx_is_lockedtodata signal goes high.

⁶⁸ t_{LTD_manual} is the time required for the receiver CDR to start recovering valid data after the rx_is_lockedtodata signal goes high when the CDR is functioning in the manual mode.

⁶⁹ t_{LTR_LTD_manual} is the time the receiver CDR must be kept in lock to reference (LTR) mode after the rx_is_lockedtoref signal goes high when the CDR is functioning in the manual mode.

⁷⁰ High Speed Differential I/O is the dedicated I/O standard for the transmitter in Intel^® Stratix^® 10 L-/H-Tile transceivers.

⁷¹ The Intel^® Quartus^® Prime software automatically selects the appropriate slew rate depending on the configured data rate or functional mode.

⁷² This specification pertains to Hyper Memory Cube.

⁷³ Intel recommends a V_OD ranging from 31 to 17.

⁷⁴ 500 ps is not supported for all configurations and depends upon the Master CGB placement.

H-Tile Transceiver Performance Specifications

Transceiver Performance for Intel Stratix 10 GX/SX/MX/TX H-Tile Devices

Table 45. Intel^® Stratix^® 10 GX/SX/MX/TX H-Tile Transmitter and Receiver Datarate Performance
Symbol	Description	Transceiver Speed Grade
Symbol	Description	-1	-2	-3
GX channels	Chip-to-chip and Backplane	17.4 Gbps
GXT channels	Chip-to-chip and Backplane	28.3 Gbps ⁷⁵	26.6 Gbps	N/A

Table 46. H-Tile ATX PLL Performance
Symbol/Description	Condition	Transceiver Speed Grade 1	Transceiver Speed Grade 2	Transceiver Speed Grade 3	Unit
Supported Output Frequency	Maximum Frequency	14.15	12.9	8.7	GHz
Supported Output Frequency	Minimum Frequency	500			MHz
t_LOCK ⁷⁶	Maximum Frequency	1			ms
t_ARESET ⁷⁷	—	25			Avalon Clock Cycles

Note: TX jitter specifications for the SerialLite III protocol at 17.4 Gbps are as low as: TJ = 0.32 UI, RJ = 0.15 UI, DJ = 0.18 UI, and DCD = 0.05 UI.

Table 47. H-Tile Fractional PLL Performance
Symbol/Description	Condition	Mode	All Transceiver Speed Grades	Unit
Supported Output Frequency (VCO frequency based)	Maximum datarate	Transceiver - HDMI	12.5	Gbps
		Transceiver - General	12.5
		Transceiver - OTN, SDI Cascade	14.025
	Minimum datarate	Transceiver - HDMI	4.6	Gbps
		Transceiver - General	6
		Transceiver - OTN, SDI Cascade	7
t_LOCK ⁷⁶	Maximum Frequency		1	ms
t_ARESET ⁷⁷	—		25	Avalon Clock Cycles

Table 48. H-Tile CMU PLL Performance
Symbol/Description	Condition	All Transceiver Speed Grades	Unit
Supported Output Frequency	Maximum Frequency	5.15625	GHz
Supported Output Frequency	Minimum Frequency	2.450	GHz
t_LOCK ⁷⁶	Maximum Frequency	1	ms
t_ARESET ⁷⁷	—	25	Avalon Clock Cycles

⁷⁵ Only four GXT channels per bank are supported for backplane applications operating at 28.3 Gbps.

⁷⁶ This specification applies after the ATX PLL, fPLL, or CMU PLL has completed calibration.

⁷⁷ You must use the Avalon-MM interface to hold the PLLs in reset for the specified cycles by writing to the ATX PLL, fPLL, or CMU PLL pll_powerdown register.

Transceiver Specifications for Intel Stratix 10 GX/SX H-Tile Devices

Table 49. H-Tile Reference Clock Specifications
Symbol/Description	Condition	Min	Typ	Max	Unit
Supported I/O Standards	Dedicated reference clock pin	CML, Differential LVPECL, LVDS, and HCSL
Supported I/O Standards	RX reference clock pin	CML, Differential LVPECL, and LVDS
Input Reference Clock Frequency (CMU PLL)		50	—	800	MHz
Input Reference Clock Frequency (ATX PLL)		100	—	800	MHz
Input Reference Clock Frequency (fPLL PLL)		50 ⁷⁸	—	800	MHz
Rise time	20% to 80%	—	—	350	ps
Fall time	80% to 20%	—	—	350	ps
Duty cycle	—	45	—	55	%
Spread-spectrum modulating clock frequency	PCIe	30	—	33	kHz
Spread-spectrum downspread	PCIe	—	0 to –0.5	—	%
On-chip termination resistors	—	—	100	—	Ω
Absolute V_MAX	Dedicated reference clock pin	—	—	1.6	V
Absolute V_MAX	RX reference clock pin	—	—	1.2	V
Absolute V_MIN	—	–0.4	—	—	V
Peak-to-peak differential input voltage	—	200	—	1600	mV
V_ICM (AC coupled)	V_{CCR_GXB} =1.03 V	—	0	—	V
V_ICM (AC coupled)	V_{CCR_GXB} = 1.12 V	—	0	—	V
V_ICM (DC coupled)	HCSL I/O standard for PCIe reference clock	250	—	550	mV
Transmitter `REFCLK` Phase Noise (800 MHz) ⁷⁹ ⁸⁰	100 Hz	—	—	–70	dBc/Hz
	1 kHz	—	—	–90	dBc/Hz
	10 kHz	—	—	–100	dBc/Hz
	100 kHz	—	—	–110	dBc/Hz
	≥ 1 MHz	—	—	–120	dBc/Hz
R_REF	—	—	2.0 k ±1%	—	Ω
T_{SSC-MAX-PERIOD-SLEW}	Max SSC df/dt			0.75

Table 50. H-Tile Transceiver Clock Network Maximum Data Rate Specifications
Clock Network	Maximum Performance ⁸¹			Channel Span	Unit
Clock Network	ATX	fPLL	CMU	Channel Span	Unit
x1	17.4	12.5	10.3125	6 channels	Gbps
x6	17.4	12.5	N/A	6 channels	Gbps
x24	17.4 ⁸⁶	12.5	N/A	2 banks up and 1 bank down (total 24 channels) or 2 banks down and 1 bank up (total 24 channels)	Gbps
GXT clock lines	28.3	N/A	N/A	4 GXT channels within the same transceiver bank and 2 from the bank above or 2 from the bank below. ⁸²	Gbps

Table 51. H-Tile Receiver Specifications
Symbol/Description	Condition	All Transceiver Speed Grades			Unit
Symbol/Description	Condition	Min	Typ	Max	Unit
Supported I/O Standards	—	High Speed Differential I/O, CML, Differential LVPECL, and LVDS
Absolute V_MAX for a receiver pin ⁸³	—	—	—	1.2	V
Absolute V_MIN for a receiver pin ⁸⁴	—	-0.4	—	—	V
Maximum peak-to-peak differential input voltage V_ID (diff p-p) before device configuration ⁸⁵	—	—	—	2.0	V
Maximum peak-to-peak differential input voltage V_ID (diff p-p) after device configuration ⁸⁵	V_{CCR_GXB} = 1.03 V, 1.12 V ⁸⁶, ⁸⁷	—	—	2.0	V
Differential on-chip termination resistors	85-Ω setting	—	85 ± 20%	—	Ω
Differential on-chip termination resistors	100-Ω setting	—	100 ± 20%	—	Ω
V_ICM (AC coupled)	V_{CCR_GXB} = 1.03 V ⁸⁷	—	700	—	mV
V_ICM (AC coupled)	V_{CCR_GXB} = 1.12 V ⁸⁷	—	750	—	mV
t_LTR ⁸⁸	—	—	—	1	ms
t_LTD ⁸⁹	—	4	—	—	µs
t_{LTD_manual} ⁹⁰	—	4	—	—	µs
t_{LTR_LTD_manual} ⁹¹	—	15	—	—	µs
Run Length	—	—	—	200	UI
CDR ppm tolerance	PCIe-only	-300	—	300	ppm
CDR ppm tolerance	All other protocols	-1000	—	1000	ppm

Table 52. H-Tile Transmitter Specifications
Symbol/Description	Condition	Transceiver Speed Grade 3			Unit
Symbol/Description	Condition	Min	Typ	Max	Unit
Supported I/O Standards	—	High Speed Differential I/O ⁹²			—
Differential on-chip termination resistors	85-Ω setting	—	85 ± 20%	—	Ω
Differential on-chip termination resistors	100-Ω setting	—	100 ± 20%	—	Ω
V_OCM (AC coupled)	V_{CCT_GXB} = 1.03 V ⁹³	—	515	—	mV
V_OCM (AC coupled)	V_{CCT_GXB} = 1.12 V ⁹³	—	560		mV
V_OCM (DC coupled)	V_{CCT_GXB} = 1.03 V ⁹³	—	515	—	mV
V_OCM (DC coupled)	V_{CCT_GXB} = 1.12 V ⁹³	—	560	—	mV
Rise time ⁹⁴	20% to 80%	20	—	130	ps
Fall time ⁹⁴	80% to 20%	20	—	130	ps
Intra-differential pair skew	TX V_CM = 0.5 V and slew rate of 15 ps	—	—	15 ⁹⁵	ps

Table 53. H-Tile Typical Transmitter V_OD Settings
Symbol	V_OD Setting ⁹⁶	V_OD/V_{CCT_GXB}Ratio
V_OD differential value = V_OD/V_{CCT_GXB} ratio x V_{CCT_GXB}	31	1.00
	30	0.97
	29	0.93
	28	0.90
	27	0.87
	26	0.83
	25	0.80
	24	0.77
	23	0.73
	22	0.70
	21	0.67
	20	0.63
	19	0.60
	18	0.57
	17	0.53
	16	0.50
	15	0.47
	14	0.43
	13	0.40
	12	0.37

Table 54. H-Tile Transmitter Channel-to-channel Skew Specifications
Mode	Channel Span	Maximum Skew	Unit
x6 Clock	Up to 6 channels in one bank	61	ps
x24 Clock	Up to 24 channels in one bank	500 ⁹⁷	ps

Table 55. Transceiver Clocks Specifications for Intel^® Stratix^® 10 GX/SX H-Tile Devices
Clock	Value	Unit
`reconfig_clk`	≤ 150	MHz
`fixed_clk` for the RX detect circuit	250 ± 20%	MHz

For OSC_CLK_1 specifications, refer to the External Configuration Clock Source Requirements section.

⁷⁸ The f_MIN is 25 MHz when the fPLL is used for the HDMI protocol.

⁷⁹ To calculate the REFCLK phase noise requirement at frequencies other than 800 MHz, use the following formula: REFCLK phase noise at f (MHz) = REFCLK phase noise at 800 MHz + 20*log(f/800).

⁸⁰ A phase noise (PN) mask overrides the REFCLK noise.

⁸¹ The maximum data rate depends on speed grade.

⁸² If the upper ATX PLL in a bank is used as the main GXT PLL, then the channel span includes two GXT channels from the bank above. If the lower ATX PLL in a bank is used as the main GXT PLL, then the channel span includes two GXT channels from the bank below.

⁸³ The device cannot tolerate prolonged operation at this absolute maximum.

⁸⁴ A passive pull up resistance prevents a 0-V common mode voltage on AC coupled receiver pins before the FPGA is configured.

⁸⁵ DC coupling specifications are pending silicon characterization.

⁸⁶ Bonded channels operating at data rates above 16 Gbps require 1.12 V ± 20 mV at the pin. For channels that are placed in the same H-Tile as the channels that required 1.12 V ± 20 mV, V_{CCR_GXB} = 1.12 V ± 20 mV.

⁸⁷ For GXT channels, V_{CCR_GXB} must be 1.12 V. For GX channels, V_{CCR_GXB} must be 1.03 V. V_{CCR_GXB} must be 1.12 V for the transceiver on the same H-Tile when using GX and GXT channels together.

⁸⁸ t_LTR is the time required for the receive CDR to lock to the input reference clock frequency after coming out of reset or after CDR calibration is completed.

⁸⁹ t_LTD is time required for the receiver CDR to start recovering valid data after the rx_is_lockedtodata signal goes high.

⁹⁰ t_{LTD_manual} is the time required for the receiver CDR to start recovering valid data after the rx_is_lockedtodata signal goes high when the CDR is functioning in the manual mode.

⁹¹ t_{LTR_LTD_manual} is the time the receiver CDR must be kept in lock to reference (LTR) mode after the rx_is_lockedtoref signal goes high when the CDR is functioning in the manual mode.

⁹² High Speed Differential I/O is the dedicated I/O standard for the transmitter in Intel^® Stratix^® 10 transceivers.

⁹³ For GXT channels, V_{CCT_GXB} must be 1.12 V. For GX channels, V_{CCT_GXB} must be 1.03 V. V_{CCT_GXB} must be 1.12 V when using GX and GXT channels together within the same H-Tile.

⁹⁴ The Intel^® Quartus^® Prime software automatically selects the appropriate slew rate depending on the configured data rate or functional mode.

⁹⁵ This specification pertains to Hyper Memory Cube.

⁹⁶ Intel recommends a V_OD ranging from 31 to 17.

⁹⁷ 500 ps is not supported for all configurations and depends upon the Master CGB placement.

E-Tile Transceiver Performance Specifications

Transceiver Performance for Intel Stratix 10 E-Tile Devices

Table 56. E-Tile Transmitter and Receiver Data Rate Performance Specifications
Symbol/Description	Condition	Minimum	Typical	Maximum	Unit
Supported datarate⁹⁸	NRZ	1		28.9	Gbps
Supported datarate⁹⁸	PAM-4	2		57.8⁹⁹	Gbps

⁹⁸ The supported datarate is for chip-to-chip and backplane links.

⁹⁹ Two channels are combined to support up to 57.8 Gbps.

Transceiver Reference Clock Specifications

Table 57. E-Tile Reference Clock LVPECL DC Electrical Characteristics
Symbol	Refclk Parameter	Minimum	Typical	Maximum	Unit
VTT	Termination Voltage (2.5V compliant)	0.4	0.5	0.6	V
VTT	Termination Voltage (3.3V compliant)	1.04	1.3	1.56	V
RTT	Termination Resistor	40	50	60	Ohm
V_DIFF	Differential Voltage	0.4	0.8	1.2	V
V_CM	Input Common Mode Voltage (2.5V compliant, no internal termination resistor)	V_DIFF/2		V_{CCCLK_GXE}-V_DIFF/2	V
V_CM	Input Common Mode Voltage (2.5V compliant, internal termination resistor)	V_{CCCLK_GXE} - 1.6	V_{CCCLK_GXE} - 1.3	V_{CCCLK_GXE} - 1.0	V
V_CM	Input Common Mode Voltage (3.3V compliant, no internal termination resistor)	V_DIFF/2		V_{CCCLK_GXE}-V_DIFF/2	V
V_CM	Input Common Mode Voltage (3.3V compliant, internal termination resistor)	1.4	2	2.6	V

Table 58. E-Tile Reference Clock Electrical & Jitter Requirements
Parameter	Condition	Minimum	Typical	Maximum	Unit

Frequency	-	125	156.25	700	MHz
Frequency Tolerance	-	-100		100	PPM
Clock Duty Cycle	-	45	50	55	%
Rise & Fall Times	20% - 80%	40		300	ps
Phase Jitter	12 KHz - 20 MHz		0.375	0.5	ps rms
Phase Noise ¹⁰⁰	10 KHz			-130	dBc/Hz
	100 KHz			-138	dBc/Hz
	500 KHz			-138	dBc/Hz
	3 MHz			-140	dBc/Hz
	10 MHz			-144	dBc/Hz
	20 MHz			-146	dBc/Hz

¹⁰⁰ The phase noise numbers in the table above are the maximum acceptable phase noise values measured at a carrier frequency of 156.25 MHz. To calculate the phase noise requirement at any other frequency, use the formula: REFCLK phase noise at f (MHz) = REFCLK phase noise at 156.25 MHz + 20*log₁₀(f/156.25)

Transmitter Specifications for Intel Stratix 10 E-Tile Devices

Table 59. E-Tile Transmitter Specifications
Symbol/Description	Condition	Minimum	Typical	Maximum	Unit
Transmitter differential output voltage peak-to-peak	No precursor/postcursor de-emphasis		0.965		V
Transmitter common mode voltage		V_{CCRT_GXE}/2			V

Receiver Specifications for Intel Stratix 10 E-Tile Devices

Table 60. E-Tile Receiver Specifications
Symbol/Description	Condition	Minimum	Typical	Maximum	Unit
Receiver run length¹⁰¹				100¹⁰²	symbols
DC input impedance		40		60	ohm
DC differential input impedance		80	100	120	ohm
Powered down DC input impedance	Receiver pin impedance when the receiver termination is powered down	100k			ohm
Electrical Idle detection voltage	-	65		175	mV
Differential termination	From DC to 100 MHz	80	100	120	ohm
PPM tolerance	Allowed frequency mismatch between REFCLK and RX data			750	ppm

¹⁰¹ No additional transition density requirements apply.

¹⁰² The incoming data must be statistically DC-balanced.

Core Performance Specifications

Clock Tree Specifications

Table 61. Clock Tree Performance for Intel^® Stratix^® 10 Devices
Parameter	Performance			Unit
Parameter	–E1V, –I1V	–E2V, –E2L, –I2V, –I2L	–E3V, –E3X, –I3V, –I3X	Unit
Programmable clock routing	1,000	900	780	MHz

PLL Specifications

Fractional PLL Specifications

Table 62. Fractional PLL Specifications for Intel^® Stratix^® 10 DevicesThese specifications are applicable when fPLL is used in core mode.
Symbol	Parameter	Condition	Min	Typ	Max	Unit
f_IN	Input clock frequency	—	29	—	800 ¹⁰³	MHz
f_INPFD	Input clock frequency to the phase frequency detector (PFD)	—	29	—	700	MHz
f_VCO	PLL voltage-controlled oscillator (VCO) operating range for core applications	—	6	—	14.025	GHz
t_EINDUTY	Input clock duty cycle	—	40	—	60	%
f_OUT	Output frequency for internal clock	—	—	—	1	GHz
f_DYCONFIGCLK	Dynamic configuration clock for `reconfig_clk`	—	—	—	125	MHz
t_LOCK	Time required to lock from end-of-device configuration	—	—	—	1	ms
t_DLOCK	Time required to lock dynamically (after switchover or reconfiguring any non-post-scale counters/delays)	—	—	—	1	ms
f_CLBW	PLL closed-loop bandwidth	—	0.3	—	4	MHz
t_INCCJ ¹⁰⁴, ¹⁰⁵	Input clock cycle-to-cycle jitter	F_REF ≥ 100 MHz	—	—	0.13	UI (p-p)
t_INCCJ ¹⁰⁴, ¹⁰⁵	Input clock cycle-to-cycle jitter	F_REF < 100 MHz	—	—	±650	ps (p-p)
t_OUTPJ ¹⁰⁶	Period jitter for clock output	F_OUT ≥ 100 MHz	—	—	600	ps (p-p)
t_OUTPJ ¹⁰⁶	Period jitter for clock output	F_OUT < 100 MHz	—	—	60	mUI (p-p)
t_OUTCCJ ¹⁰⁶	Cycle-to-cycle jitter for clock output	F_OUT ≥ 100 MHz	—	—	600	ps (p-p)
t_OUTCCJ ¹⁰⁶	Cycle-to-cycle jitter for clock output	F_OUT < 100 MHz	—	—	60	mUI (p-p)
dK_BIT	Bit number of Delta Sigma Modulator (DSM)	—	—	32	—	bit

¹⁰³ This specification is limited by the I/O maximum frequency. The maximum achievable I/O frequency is different for each I/O standard and is dependent on design and system specific factors. Ensure proper timing closure in your design and perform HSPICE/IBIS simulations based on your specific design and system setup to determine the maximum achievable frequency in your system.

¹⁰⁴ A high input jitter directly affects the PLL output jitter. To have low PLL output clock jitter, you must provide a clean clock source with jitter < 120 ps.

¹⁰⁵ F_REF is f_IN/N, specification applies when N = 1.

¹⁰⁶ External memory interface clock output jitter specifications use a different measurement method, which are available in Memory Output Clock Jitter Specifications for Intel^® Stratix^® 10 Devices table.

I/O PLL Specifications

Table 63. I/O PLL Specifications for Intel^® Stratix^® 10 Devices
Symbol	Parameter	Condition	Min	Typ	Max	Unit
f_IN	Input clock frequency	–1 speed grade	10	—	1,100 ¹⁰⁷	MHz
		–2 speed grade	10	—	900 ¹⁰⁷	MHz
		–3 speed grade	10	—	750 ¹⁰⁷	MHz
f_INPFD	Input clock frequency to the PFD	—	10	—	325	MHz
f_VCO	PLL VCO operating range	–1 speed grade	600	—	1,600	MHz
		–2 speed grade	600	—	1,434	MHz
		–3 speed grade	600	—	1,280 ¹⁰⁸	MHz
f_CLBW	PLL closed-loop bandwidth	—	0.5	—	10	MHz
t_EINDUTY	Input clock or external feedback clock input duty cycle	—	40	—	60	%
f_OUT	Output frequency for internal clock (`C` counter)	–1 speed grade	—	—	1,100	MHz
		–2 speed grade	—	—	900	MHz
		–3 speed grade	—	—	750	MHz
f_{OUT_EXT}	Output frequency for external clock output	–1 speed grade	—	—	800	MHz
		–2 speed grade	—	—	720	MHz
		–3 speed grade	—	—	650	MHz
t_OUTDUTY	Duty cycle for dedicated external clock output (when set to 50%)	—	45	50	55	%
t_FCOMP	External feedback clock compensation time	—	—	—	5	ns
f_DYCONFIGCLK	Dynamic configuration clock for `mgmt_clk` and `scanclk`	—	—	—	200	MHz
t_LOCK	Time required to lock from end-of-device configuration or deassertion of `areset`	—	—	—	1	ms
t_DLOCK	Time required to lock dynamically (after switchover or reconfiguring any non-post-scale counters/delays)	—	—	—	1	ms
t_{PLL_PSERR}	Accuracy of PLL phase shift	—	—	—	±50	ps
t_ARESET	Minimum pulse width on the `areset` signal	—	10	—	—	ns
t_INCCJ ¹⁰⁹ ¹¹⁰	Input clock cycle-to-cycle jitter	F_REF ≥ 100 MHz	—	—	0.15	UI (p-p)
t_INCCJ ¹⁰⁹ ¹¹⁰	Input clock cycle-to-cycle jitter	F_REF < 100 MHz	—	—	±750	ps (p-p)
t_{OUTPJ_DC}	Period jitter for dedicated clock output	F_OUT ≥ 100 MHz	—	—	175	ps (p-p)
t_{OUTPJ_DC}	Period jitter for dedicated clock output	F_OUT < 100 MHz	—	—	17.5	mUI (p-p)
t_{OUTCCJ_DC}	Cycle-to-cycle jitter for dedicated clock output	F_OUT ≥ 100 MHz	—	—	175	ps (p-p)
t_{OUTCCJ_DC}	Cycle-to-cycle jitter for dedicated clock output	F_OUT < 100 MHz	—	—	17.5	mUI (p-p)
t_{OUTPJ_IO} ¹¹¹	Period jitter for clock output on the regular I/O	F_OUT ≥ 100 MHz	—	—	600	ps (p-p)
t_{OUTPJ_IO} ¹¹¹	Period jitter for clock output on the regular I/O	F_OUT < 100 MHz	—	—	60	mUI (p-p)
t_{OUTCCJ_IO} ¹¹¹	Cycle-to-cycle jitter for clock output on the regular I/O	F_OUT ≥ 100 MHz	—	—	600	ps (p-p)
t_{OUTCCJ_IO} ¹¹¹	Cycle-to-cycle jitter for clock output on the regular I/O	F_OUT < 100 MHz	—	—	60	mUI (p-p)
t_{CASC_OUTPJ_DC}	Period jitter for dedicated clock output in cascaded PLLs through dedicated cascade path and core clock fabric	F_OUT ≥ 100 MHz	—	—	175	ps (p-p)
t_{CASC_OUTPJ_DC}		F_OUT < 100 MHz	—	—	17.5	mUI (p-p)

¹⁰⁷ This specification is limited by the I/O maximum frequency. The maximum achievable I/O frequency is different for each I/O standard and is dependent on design and system specific factors. Ensure proper timing closure in your design and perform HSPICE/IBIS simulations based on your specific design and system setup to determine the maximum achievable frequency in your system.

¹⁰⁸ This specification is only applicable when the I/O PLL is instantiated with the IOPLL Intel^® FPGA IP core. For I/O PLL instantiated with LVDS SERDES Intel^® FPGA IP core, PHY Lite for Parallel Interfaces Intel Stratix 10 FPGA IP core, External Memory Interfaces Intel Stratix 10 FPGA IP core, and High Bandwidth Memory (HBM-2) Interface Intel^® FPGA IP core, the maximum f_VCO is 1,250 MHz.

¹⁰⁹ A high input jitter directly affects the PLL output jitter. To have low PLL output clock jitter, you must provide a clean clock source with jitter < 120 ps.

¹¹⁰ F_REF is f_IN/N, specification applies when N = 1.

¹¹¹ External memory interface clock output jitter specifications use a different measurement method, which are available in Memory Output Clock Jitter Specifications for Intel^® Stratix^® 10 Devices table.

DSP Block Specifications

Table 64. DSP Block Performance Specifications for Intel^® Stratix^® 10 Devices
Mode	Performance			Unit
Mode	–E1V, –I1V	–E2V, –E2L, –I2V, –I2L	–E3V, –E3X, –I3V, –I3X	Unit
Fixed-point 18 × 19 multiplication mode	1,000	771	667	MHz
Fixed-point 27 × 27 multiplication mode ¹¹²	1,000	771	667	MHz
Fixed-point 18 × 18 multiplier adder mode ¹¹²	1,000	771	667	MHz
Fixed-point 18 × 18 multiplier adder summed with 36-bit input mode ¹¹²	1,000	771	667	MHz
Fixed-point 18 × 19 systolic mode	1,000	771	667	MHz
Complex 18 × 19 multiplication mode	1,000	771	667	MHz
Floating point multiplication mode	750	579	500	MHz
Floating point adder or subtract mode	750	579	500	MHz
Floating point multiplier adder or subtract mode	750	579	500	MHz
Floating point multiplier accumulate mode	750	579	500	MHz
Floating point vector one mode	750	579	500	MHz
Floating point vector two mode	750	579	500	MHz

¹¹² When chainin or chainout is enabled, the performance specifications for the following speed grades are as follows:

–E1V and –I1V: 750 MHz
–E2V, –E2L, –I2V, and –I2L: 578 MHz
–E3V, –E3X, –I3V, and –I3X: 507 MHz

Memory Block Specifications

To achieve the maximum memory block performance, use a memory block clock that comes through global clock routing from an on-chip PLL and set to 50% output duty cycle. Use the Intel^® Quartus^® Prime software to report timing for the memory block clocking schemes.

When you use the error detection cyclical redundancy check (CRC) feature, there is no degradation in f_MAX.

Table 65. Memory Block Performance Specifications for Intel^® Stratix^® 10 Devices
Memory	Mode	Performance
Memory	Mode	–E1V, –I1V	–E2V, –E2L, –I2V, –I2L	–E3V, –E3X, –I3V, –I3X	Unit
MLAB	Single port, all supported widths (×16/×32)	1,000	782	667	MHz
	Simple dual-port, all supported widths (×16/×32)	1,000	782	667	MHz
	Simple dual-port with read-during-write option	550	450	400	MHz
	ROM, all supported width (×16/×32)	1,000	782	667	MHz
M20K Block	Single-port, all supported widths	1,000	782	667	MHz
	Simple dual-port, all supported widths	1,000	782	667	MHz
	Simple dual-port, coherent read enabled	1,000	782	667	MHz
	Simple dual-port with the read-during-write option set to Old Data, all supported widths	800	640	560	MHz
	Simple dual-port with ECC enabled, 512 × 32	600	480	420	MHz
	Simple dual-port with ECC, optional pipeline registers enabled, and fast write mode, 512 × 32	1,000	782	667	MHz
	Simple dual-port with ECC and optional pipeline registers enabled, with the read-during-write option set to Old Data, 512 × 32	1,000	750	667	MHz
	True dual port, all supported widths	600	500	420	MHz
	Simple quad-port, all supported widths	600	480	420	MHz
	ROM, all supported widths	1,000	782	667	MHz
eSRAM ¹¹³ ¹¹⁴	Simple dual-port	200–750	200–640	200–500	MHz

¹¹³ The input clock source for eSRAM must not exceed 20 ps peak-to-peak, or 1.42 ps RMS at 1e^–12 BER or 1.22 ps at 1e^–16 BER.

¹¹⁴ For speed grade –3 devices, the following clock frequency ranges are not supported:

466.51 MHz – 499.99 MHz
233.26 MHz – 249.99 MHz

Internal Temperature Sensing Diode Specifications

Table 66. Internal Temperature Sensing Diode Specifications for Intel^® Stratix^® 10 Devices
Temperature Range	Accuracy	Offset Calibrated Option	Sampling Rate	Conversion Time
–40 to 125 °C ¹¹⁵	±5 °C	No	1 KSPS	< 1 ms

¹¹⁵ Temperature range refers to junction temperature.

External Temperature Sensing Diode Specifications

Table 67. External Temperature Sensing Diode Specifications for Intel^® Stratix^® 10 Devices

The typical value is at 25°C.

Diode accuracy improves with lower injection current.

Absolute accuracy is dependent on third-party external diode ADC and integration specifics.
Description	Min	Typ	Max	Unit
I_bias, diode source current	10	—	100	μA
V_bias, voltage across diode	0.35	—	0.9	V
Series resistance (core fabric TSD)	—	—	< 3	Ω
Series resistance (L-Tile and H-Tile TSD)	—	—	< 1	Ω
Series resistance (E-Tile TSD)	—	—	¹¹⁶	Ω
Diode ideality factor (core fabric TSD)	—	1.006	—	—
Diode ideality factor (L-Tile and H-Tile TSD)	—	1.03	—	—
Diode ideality factor (E-Tile TSD)	—	¹¹⁶	—	—

¹¹⁶ Pending silicon characterization.

Internal Voltage Sensor Specifications

Table 68. Internal Voltage Sensor Specifications for Intel^® Stratix^® 10 Devices
Parameter		Minimum	Typical	Maximum	Unit
Resolution		—	8	—	Bit
Sampling rate		—	—	1.0	KSPS
Differential non-linearity (DNL)		—	—	±1	LSB
Integral non-linearity (INL)		—	—	±1	LSB
Input capacitance		—	—	40	pF
Voltage sensor accuracy, V_in range: 0 V to 1.24 V		–3	—	3	%
Unipolar Input Mode	Input signal range for Vsigp	0	—	1.49	V
	Common mode voltage on Vsign	0	—	0.25	V
	Input signal range for Vsigp – Vsign	0	—	1.24	V

HPS Performance Specifications

This section provides hard processor system (HPS) specifications and timing for Intel^® Stratix^® 10 devices.

HPS Clock Performance

Table 69. Maximum HPS Clock Frequencies for Intel^® Stratix^® 10 Devices
Performance	V_{CCL_HPS} (V)	MPU Frequency (MHz)	SDRAM Interconnect Frequency¹¹⁷ (MHz)	L3 Interconnect Frequency (MHz)
–E1V, –I1V	SmartVID	1,200	533	400
	0.9	1,200	533	400
	0.94	1,350	533	400 ¹¹⁸
–E2V, –I2V	SmartVID	1,000	467	400
	0.9	1,000	467	400
	0.94	1,000	467	400
–E3V, –I3V	SmartVID	800	400	333
	0.9	800	400	333
	0.94	800	400	400
–E2L, –I2L ¹¹⁹	0.9	1200	467	400
–E2L, –I2L ¹¹⁹	0.94	1,350	467	400 ¹¹⁸
–E3X, –I3X ¹¹⁹	0.9	1,200	400	400
–E3X, –I3X ¹¹⁹	0.94	1,350	400	400 ¹¹⁸

¹¹⁷ This frequency is for the hmc_free_clk, which is half the frequency of the HPS external memory interface (EMIF).

¹¹⁸ If MPU frequency is 1,350 MHz, the L3 interconnect frequency is 385 MHz because of the clock ratios.

¹¹⁹

Note that V_{CCL_HPS} can not be connected to SmartVID for –E2L, –I2L, –E3X, and –I3X devices.

HPS Internal Oscillator Frequency

Table 70. HPS Internal Oscillator Frequency for Intel^® Stratix^® 10 Devices
Description	Min	Typ	Max	Unit
Internal Oscillator Frequency	100	200	300	MHz

HPS PLL Specifications

HPS PLL Input Requirements

Table 71. HPS PLL Input Requirements for Intel^® Stratix^® 10 DevicesThe main HPS PLL receives its clock signals from the `HPS_OSC_CLK` pin. Refer to the *Intel Stratix 10 Device Family Pin Connection Guidelines* for information about assigning this pin.
Description	Min	Typ	Max	Unit
Clock input range	25	—	125	MHz
Clock input accuracy	—	—	50	PPM
Clock input duty cycle	45	50	55	%

HPS PLL Performance

Table 72. HPS PLL Performance for Intel^® Stratix^® 10 Devices
Description	Min	Max	Unit
Main PLL VCO output	—	3000	MHz
Peripheral PLL VCO output	—	3000	MHz
h2f_user0_clk ¹²⁰	—	500	MHz
h2f_user1_clk ¹²⁰	—	500	MHz

¹²⁰ The HPS PLL provides this clock to the FPGA fabric.

HPS SPI Timing Characteristics

Table 73. SPI Master Timing Requirements for Intel^® Stratix^® 10 DevicesYou can adjust the input delay timing by programming the `rx_sample_dly` register.
Symbol	Description	Min	Typ	Max	Unit
T_{spi_ref_clk}	The period of the SPI internal reference clock, sourced from `l4_main_clk`	2.5	—	—	ns
T_clk	SPIM_CLK clock period	16.67	—	—	ns
T_dutycycle	SPIM_CLK duty cycle	45	50	55	%
T_{ck_jitter}	SPIM_CLK output jitter	—	—	2	%
T_dio	Master-out slave-in (MOSI) output skew	–3	—	2	ns
T_dssfrst ¹²¹	SPI_SS_N asserted to first SPIM_CLK edge	(1.5 × T_clk) – 2	—	—	ns
T_dsslst ¹²¹	Last SPIM_CLK edge to SPI_SS_N deasserted	T_clk – 2	—	—	ns
T_su ¹²²	SPIM_MISO setup time with respect to SPIM_CLK capture edge	4 .5 – ( `rx_sample_dly` × T _{spi_ref_clk} ) ¹²³	—	—	ns
T_h ¹²²	Input hold in respect to SPIM_CLK capture edge	1.3 + (`rx_sample_dly`× T_{spi_ref_clk})	—	—	ns

Figure 8. SPI Master Output Timing Diagram

Figure 9. SPI Master Input Timing Diagram

Table 74. SPI Slave Timing Requirements for Intel^® Stratix^® 10 Devices
Symbol	Description	Min	Typ	Max	Unit
T_{spi_ref_clk}	The period of the SPI internal reference clock, sourced from `l4_main_clk`	2.5	—	—	ns
T_clk	SPIM_CLK clock period	30	—	—	ns
T_dutycycle	SPIM_CLK duty cycle	45	50	55	%
T_d	Master-in slave-out (MISO) output skew	(2 × T_{spi_ref_clk}) + 3	—	(3 × T_{spi_ref_clk}) + 11	ns
T_su	Master-out slave-in (MOSI) setup time	4	—	—	ns
T_h	Master-out slave-in (MOSI) hold time	9	—	—	ns
T_suss	SPI_SS_N asserted to first SPIM_CLK edge	T_{spi_ref_clk} + 4	—	—	ns
T_hss	Last SPIM_CLK edge to SPI_SS_N deasserted	T_{spi_ref_clk} + 4	—	—	ns

Figure 10. SPI Slave Output Timing Diagram

Figure 11. SPI Slave Input Timing Diagram

¹²¹ SPI_SS_N behavior differs depending on Motorola SPI, TI SSP or Microwire operational mode.

¹²² The capture edge differs depending on the operational mode. For Motorola SPI, the capture edge can be the rising or falling edge depending on the scpol register bit; for TI SSP, the capture edge is the falling edge; for Microwire, the capture edge is the rising edge.

¹²³ Valid values of rx_sample_dly range from 1 to 64 (units are in T _{spi_ref_clk} steps)

HPS SD/MMC Timing Characteristics

Table 75. HPS Secure Digital (SD)/MultiMediaCard (MMC) Timing Requirements for Intel^® Stratix^® 10 DevicesThese timings apply to SD, MMC, and embedded MMC (eMMC) cards operating at 1.8 V.
Symbol	Description	Min	Typ	Max	Unit
T_{sdmmc_cclk}	SDMMC_CCLK clock period (Identification mode)	2500	—	—	ns
	SDMMC_CCLK clock period (SDR12)	40	—	—	ns
	SDMMC_CCLK clock period (SDR25)	20	—	—	ns
T_dutycycle	SDMMC_CCLK duty cycle	45	50	55	%
T_{sdmmc_cclk_jitter}	SDMMC_CCLK output jitter	—	—	2	%
T_{sdmmc_clk}	Internal reference clock before division by 4	5	—	—	ns
T_d	SDMMC_CMD/SDMMC_DATA[7:0] output delay ¹²⁴	T_{sdmmc_clk} × `drvsel`/2	—	3 + (T_{sdmmc_clk} × `drvsel`/2)	ns
T_su	SDMMC_CMD/SDMMC_DATA[7:0] input setup ¹²⁵	6 – (T_{sdmmc_clk} × `smplsel`/2)	—	—	ns
T_h	SDMMC_CMD/SDMMC_DATA[7:0] input hold ¹²⁵	0.5 + (T_{sdmmc_clk} × `smplsel`/2)	—	—	ns

None of the HPS I/Os supports 3 V mode, while SD/MMC cards must operate at 3 V at power on. eMMC devices can operate at 1.8 V at power on.

Note: SD cards power up at 3 V. To support SD, your design must include a level shifter between the SD card and the HPS SD/MMC interface.

Figure 12. SD/MMC Timing Diagram

¹²⁴ When the drvsel bitfield in the sdmmc register is set to 3 (in the system manager) and the reference clock (sdmmc_clk) is 200 MHz for example, the output delay time is 7.5 to 10.5 ns.

¹²⁵ When the smplsel bitfield in the sdmmc register is set to 2 (in the system manager) and the reference clock (sdmmc_clk) is 200 MHz for example, the setup time is 1 ns and the hold time is 5.5 ns.

HPS USB UPLI Timing Characteristics

Table 76. HPS USB 2.0 Transceiver Macrocell Interface Plus (UTMI+) Low Pin Interface (ULPI) Timing Requirements for Intel^® Stratix^® 10 Devices
Symbol	Description	Min	Typ	Max	Unit
T_{usb_clk}	USB_CLK clock period	—	16.667	—	ns
T_d	Clock to USB_STP/USB_DATA[7:0] output delay	2	—	7	ns
T_su	Setup time for USB_DIR/USB_NXT/USB_DATA[7:0]	4	—	—	ns
T_h	Hold time for USB_DIR/USB_NXT/USB_DATA[7:0]	1	—	—	ns

Figure 13. USB ULPI Timing Diagram

Note: The USB interface supports single data rate (SDR) timing only.

HPS Ethernet Media Access Controller (EMAC) Timing Characteristics

Table 77. Reduced Gigabit Media Independent Interface (RGMII) TX Timing Requirements for Intel^® Stratix^® 10 Devices
Symbol	Description	Min	Typ	Max	Unit
T_clk (1000Base-T)	TX_CLK clock period	—	8	—	ns
T_clk (100Base-T)	TX_CLK clock period	—	40	—	ns
T_clk (10Base-T)	TX_CLK clock period	—	400	—	ns
T_dutycycle (1000Base-T)	TX_CLK duty cycle	45	50	55	%
T_dutycycle(10/100Base-T)	TX_CLK duty cycle	40	50	60	%
T_d ¹²⁶ ¹²⁷	TXD/TX_CTL to TX_CLK output skew	–0.5	—	0.5	ns

Figure 14. RGMII TX and RMII TX Timing Diagram

Table 78. RGMII RX Timing Requirements for Intel^® Stratix^® 10 Devices
Symbol	Description	Min	Typ	Max	Unit
T_clk (1000Base-T)	RX_CLK clock period	—	8	—	ns
T_clk (100Base-T)	RX_CLK clock period	—	40	—	ns
T_clk (10Base-T)	RX_CLK clock period	—	400	—	ns
T_dutycycle(1000Base-T)	RX_CLK duty cycle	45	50	55	%
T_dutycycle(10/100Base-T)	RX_CLK duty cycle	40	50	60	%
T_su	RX_D/RX_CTL to RX_CLK setup time	1	—	—	ns
T_h ¹²⁸	RX_CLK to RX_D/RX_CTL hold time	1	—	—	ns

Figure 15. RGMII RX and RMII RX Timing Diagram

Table 79. Reduced Media Independent Interface (RMII) Clock Timing Requirements for Intel^® Stratix^® 10 Devices
Symbol	Description	Min	Typ	Max	Unit
T_clk	REF_CLK clock period, sourced by HPS TX_CLK	—	20	—	ns
T_clk	REF_CLK clock period, sourced by external clock source	—	20	—	ns
T_{dutycycle_int}	Clock duty cycle, REF_CLK sourced by TX_CLK	35	50	65	%
T_{dutycycle_ext}	Clock duty cycle, REF_CLK sourced by external clock source	35	50	65	%

Table 80. RMII TX Timing Requirements for Intel^® Stratix^® 10 Devices
Symbol	Description	Min	Typ	Max	Unit
T_d	TX_CLK to TXD/TX_CTL output data delay	2	—	10	ns

Table 81. RMII RX Timing Requirements for Intel^® Stratix^® 10 Devices
Symbol	Description	Min	Typ	Max	Unit
T_su	RX_D/RX_CTL setup time	2	—	—	ns
T_h	RX_D/RX_CTL hold time	1	—	—	ns

Table 82. Management Data Input/Output (MDIO) Timing Requirements for Intel^® Stratix^® 10 Devices
Symbol	Description	Min	Typ	Max	Unit
T_clk	MDC clock period	400	—	—	ns
T_d	MDC to MDIO output data delay	10	—	300	ns
T_su	Setup time for MDIO data	10	—	—	ns
T_h	Hold time for MDIO data	0	—	—	ns

Figure 16. MDIO Timing Diagram

¹²⁶ Rise and fall times depend on the I/O standard, drive strength, and loading. Intel recommends simulating your configuration.

¹²⁷ If you connect a PHY that does not implement clock-to-data skew, you can delay TX_CLK by 1.5—2.0 ns with the HPS I/O programmable delay, to meet the PHY's 1-ns data-to-clock skew requirement.

¹²⁸

If you connect a PHY that does not implement clock-to-data skew, you can meet the HPS EMAC’s 1 ns setup time by delaying RX_CLK by 1.5-2 ns, using the HPS I/O programmable delay.

HPS I2C Timing Characteristics

Table 83. HPS I²C Timing Requirements for Intel^® Stratix^® 10 Devices
Symbol	Description	Standard Mode		Fast Mode		Unit
Symbol	Description	Min	Max	Min	Max	Unit
T_clk	Serial clock (SCL) clock period	10	—	2.5	—	μs
T_{clk_jitter}	I2C clock output jitter	—	2	—	2	%
T_HIGH ¹²⁹	SCL high period	4 ¹³⁰	—	0.6 ¹³¹	—	μs
T_LOW ¹³²	SCL low period	4.7 ¹³³	—	1.3 ¹³⁴	—	μs
T_SU;DAT	Setup time for serial data line (SDA) data to SCL	0.25	—	0.1	—	μs
T_HD;DAT ¹³⁵	Hold time for SCL to SDA data	0	3.15	0	0.6	μs
T_VD;DAT and T_VD;ACK ¹³⁶	SCL to SDA output data delay	—	3.45 ¹³⁷	—	0.9 ¹³⁸	μs
T_SU;STA	Setup time for a repeated start condition	4.7	—	0.6	—	μs
T_HD;STA	Hold time for a repeated start condition	4	—	0.6	—	μs
T_SU;STO	Setup time for a stop condition	4	—	0.6	—	μs
T_BUF	SDA high pulse duration between STOP and START	4.7	—	1.3	—	μs
T_scl:r ¹³⁹	SCL rise time	—	1000	20	300	ns
T_scl:f ¹³⁹	SCL fall time	—	300	6.54	300	ns
T_sda:r ¹³⁹	SDA rise time	—	1000	20	300	ns
T_sda:f ¹³⁹	SDA fall time	—	300	6.54	300	ns

Figure 17. I²C Timing Diagram

¹²⁹ You can adjust T_high using the ic_ss_scl_hcnt or ic_fs_scl_hcnt register.

¹³⁰ The recommended minimum setting for ic_ss_scl_hcnt is 440.

¹³¹ The recommended minimum setting for ic_fs_scl_hcnt is 71.

¹³² You can adjust T_low using the ic_ss_scl_lcnt or ic_fs_scl_lcnt register.

¹³³ The recommended minimum setting for ic_ss_scl_lcnt is 500.

¹³⁴ The recommended minimum setting for ic_fs_scl_lcnt is 141.

¹³⁵ T_HD;DAT is affected by the rise and fall time.

¹³⁶ T_VD;DAT and T_VD;ACK are affected by the rise and fall time, as well as the SDA hold time (set by adjusting the ic_sda_hold register).

¹³⁷ Use maximum SDA_HOLD = 240 to be within the specification.

¹³⁸ Use maximum SDA_HOLD = 60 to be within the specification.

¹³⁹ Rise and fall time parameters vary depending on external factors such as the characteristics of the IO driver, pull-up resistor value, and total capacitance on the transmission line.

HPS NAND Timing Characteristics

Table 84. HPS NAND ONFI 1.0 Timing Requirements for Intel^® Stratix^® 10 Devices
Symbol	Description	Min	Max	Unit
T_WP ¹⁴⁰	Write enable pulse width	10	—	ns
T_WH ¹⁴⁰	Write enable hold time	7	—	ns
T_RP ¹⁴⁰	Read enable pulse width	10	—	ns
T_REH ¹⁴⁰	Read enable hold time	7	—	ns
T_CLS ¹⁴⁰	Command latch enable to write enable setup time	10	—	ns
T_CLH ¹⁴⁰	Command latch enable to write enable hold time	5	—	ns
T_CS ¹⁴⁰	Chip enable to write enable setup time	15	—	ns
T_CH ¹⁴⁰	Chip enable to write enable hold time	5	—	ns
T_ALS ¹⁴⁰	Address latch enable to write enable setup time	10	—	ns
T_ALH ¹⁴⁰	Address latch enable to write enable hold time	5	—	ns
T_DS ¹⁴⁰	Data to write enable setup time	7	—	ns
T_DH ¹⁴⁰	Data to write enable hold time	5	—	ns
T_WB ¹⁴⁰	Write enable high to R/B low	—	200	ns
T_CEA	Chip enable to data access time	—	100	ns
T_REA	Read enable to data access time	—	40	ns
T_RHZ	Read enable to data high impedance	—	200	ns
T_RR	Ready to read enable low	20	—	ns

Figure 18. NAND Command Latch Timing Diagram

Figure 19. NAND Address Latch Timing Diagram

Figure 20. NAND Data Output Cycle Timing Diagram

Figure 21. NAND Data Input Cycle Timing Diagram

Figure 22. NAND Data Input Timing Diagram for Extended Data Output (EDO) Cycle

Figure 23. NAND Read Status Timing Diagram

Figure 24. NAND Read Status Enhanced Timing Diagram

¹⁴⁰ This timing is software programmable. Refer to the NAND Flash Controller chapter in the Stratix 10 Hard Processor System Technical Reference Manual for more information about software-programmable timing in the NAND flash controller.

HPS Trace Timing Characteristics

Table 85. Trace Timing Requirements for Intel^® Stratix^® 10 Devices
To increase the trace bandwidth, Intel^® recommends routing the trace interface to the FPGA in the HPS Platform Designer (Standard) component. The FPGA trace interface offers a 64-bit single data rate path that can be converted to double data rate to minimize FPGA I/O usage.

Depending on the trace module that you connect to the HPS trace interface, you may need to include board termination to achieve the maximum sampling speed possible. Refer to your trace module datasheet for termination recommendations.

Most trace modules implement programmable clock and data skew, to improve trace data timing margins. Alternatively, you can change the clock-to-data timing relationship with the HPS programmable I/O delay.
Symbol	Description	Min	Typ	Max	Unit
T_clk	Trace clock period	6.667	—	—	ns
T_{clk_jitter}	Trace clock output jitter	—	—	2	%
T_dutycycle	Trace clock maximum duty cycle	45	50	55	%
T_d	T_clk to D0–D15 output data delay	0	—	1.8	ns

Figure 25. Trace Timing Diagram

HPS GPIO Interface

The general-purpose I/O (GPIO) interface has debounce circuitry included to remove signal glitches. The debounce clock frequency ranges from 125 Hz to 32 kHz. The minimum pulse width is 1 debounce clock cycle and the minimum detectable GPIO pulse width is 62.5 µs (at 32 kHz). Any pulses shorter than 2 debounce clock cycles are filtered by the GPIO peripheral.

If the external signal is driven into the GPIO for less than one clock cycle, the external signal is filtered. If the external signal is between one and two clock cycles, the external signal may or may not be filtered depending on the phase of the signal. If the external signal is more than two clock cycles, the external signal is not filtered.

HPS JTAG Timing Characteristics

Table 86. HPS JTAG Timing Requirements for Intel^® Stratix^® 10 Devices
Symbol	Description	Min	Typ	Max	Unit
t_JCP	TCK clock period	41.66	—	—	ns
t_JCH	TCK clock high time	20	—	—	ns
t_JCL	TCK clock low time	20	—	—	ns
t_JPSU (TDI)	TDI JTAG port setup time	5	—	—	ns
t_JPSU (TMS)	TMS JTAG port setup time	5	—	—	ns
t_JPH	JTAG port hold time	0	—	—	ns
t_JPCO	JTAG port clock to output	0	—	8	ns
t_JPZX	JTAG port high impedance to valid output	—	—	10	ns
t_JPXZ	JTAG port valid output to high impedance	—	—	10	ns

HPS Programmable I/O Timing Characteristics

Table 87. HPS Programmable I/O Delay for Intel^® Stratix^® 10 Device
Programmable Delay	Description	Min	Typ	Max	Unit
0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30	No delay enabled	—	0	—	ps
1	Delay Step 1	—	120	—	ps
3	Delay Step 2	—	240	—	ps
5	Delay Step 3	—	360	—	ps
7	Delay Step 4	—	480	—	ps
9	Delay Step 5	—	600	—	ps
11	Delay Step 6	—	720	—	ps
13	Delay Step 7	—	840	—	ps
15	Delay Step 8	—	960	—	ps
17	Delay Step 9	—	1080	—	ps
19	Delay Step 10	—	1200	—	ps
21	Delay Step 11	—	1320	—	ps
23	Delay Step 12	—	1440	—	ps
25	Delay Step 13	—	1560	—	ps
27	Delay Step 14	—	1680	—	ps
29	Delay Step 15	—	1800	—	ps
31	Delay Step 16	—	1920	—	ps

You can program the number of delay steps by adjusting the I/O Delay register (io0_delay through io47_delay for I/Os 0 through 47).

Configuration Specifications

General Configuration Timing Specifications

Table 88. General Configuration Timing Specifications for Intel^® Stratix^® 10 Devices
Symbol	Description		Requirement			Unit
Symbol	Description		Min	Typ	Max	Unit
t_CF12ST1 ¹⁴¹	`nCONFIG` high to `nSTATUS` high		—	10	—	ms
t_CF02ST0	`nCONFIG` low to `nSTATUS` low	Device is empty or not yet configured	—	10	100	ms
t_CF02ST0	`nCONFIG` low to `nSTATUS` low	Device is configured	—	200	400	ms
t_ST0	`nSTATUS` low pulse during configuration error		0.5	—	1.5	ms
t_CD2UM ¹⁴²	`CONF_DONE` high to user mode		—	—	2	ms

¹⁴¹ The maximum time does not exceed 2× of the typical value.

¹⁴² This specification is the initialization time that indicates the time from CONF_DONE signal goes high to INIT_DONE signal goes high.

POR Specifications

Power-on reset (POR) delay is defined as the delay between the time when all the power supplies monitored by the POR circuitry reach the minimum recommended operating voltage to the time when the nSTATUS is released high and your device is ready to begin configuration.

Table 89. POR Delay Specification for Intel^® Stratix^® 10 Devices
POR Delay	Minimum	Maximum	Unit
AS (Normal mode), AVST ×8, AVST ×16, AVST ×32, SD/MMC	12	20	ms
AS (Fast mode)	2	6.5	ms

External Configuration Clock Source Requirements

Table 90. External Configuration Clock Source (OSC_CLK_1) Clock Input Requirements
Description	External Clock Source	Min	Typ	Max	Unit
Clock input frequency ¹⁴³	Powered by V_{CCIO_SDM}	25/100/125			MHz
Clock input jitter tolerance		—	—	2	%
Clock input duty cycle		45	50	55	%

¹⁴³ The acceptable clock frequencies are 25 MHz, 100 MHz, and 125 MHz only. You must match the external configuration clock frequency on the OSC_CLK_1 pin to the configuration clock source assignment in the Intel^® Quartus^® Prime software. Other frequencies in the range are not supported.

JTAG Configuration Timing

Table 91. JTAG Timing Parameters and Values for Intel^® Stratix^® 10 Devices
Symbol	Description	Requirement		Unit
Symbol	Description	Minimum	Maximum	Unit
t_JCP	`TCK` clock period	30	—	ns
t_JCH	`TCK` clock high time	14	—	ns
t_JCL	`TCK` clock low time	14	—	ns
t_{JPSU (TDI)}	`TDI` JTAG port setup time	2	—	ns
t_{JPSU (TMS)}	`TMS` JTAG port setup time	3	—	ns
t_JPH	JTAG port hold time	5	—	ns
t_JPCO	JTAG port clock to output	—	7	ns
t_JPZX	JTAG port high impedance to valid output	—	14	ns
t_JPXZ	JTAG port valid output to high impedance	—	14	ns

Figure 26. JTAG Timing Diagram

AS Configuration Timing

Table 92. AS Timing Parameters for Intel^® Stratix^® 10 Devices Intel recommends performing trace length matching for `nCSO` and `AS_DATA` pins to `AS_CLK` to minimize the skew. The maximum tolerance for skew between `nCSO` and `AS_CLK` is recommended to be less than 200 ps. The tolerance for skew between `AS_CLK` to `AS_DATA` must be within 0 ps – 400 ps.
Symbol	Description		Minimum	Typical	Maximum	Unit
T_clk	`AS_CLK` clock period		—	7.52	—	ns
T_dutycycle	`AS_CLK` duty cycle		45	50	55	%
T_dcsfrs	`AS_nCSO[3:0]` asserted to first `AS_CLK` edge		4.21 ¹⁴⁴	—	7.50 ¹⁴⁴	ns
T_dcslst	Last `AS_CLK` edge to `AS_nCSO[3:0]` deasserted		5.18 ¹⁴⁴	—	8 ¹⁴⁴	ns
T_do	`AS_DATA0` output delay		–1.5	—	1.31	ns
T_{ext_delay} ¹⁴⁵	Total external propagation delay on AS signals		0	—	15	ns
T_{ext_skew}	Skew delay for AS_DATA signals for the specific `AS_CLK` frequency	133 MHz	—	—	4.61	ns
		125 MHz	—	—	5.09	ns
		115 MHz	—	—	5.79	ns
		108 MHz	—	—	6.35	ns
		100 MHz	—	—	7.09	ns
		80 MHz	—	—	9.59	ns
		77 MHz	—	—	7.92	ns
		58 MHz	—	—	10.02	ns
		50 MHz	—	—	12.09	ns
		25 MHz	—	—	22.09	ns
T_dcsb2b	Minimum delay of slave select deassertion between two back-to-back transfers		1	—	—	`AS_CLK`

Figure 27. AS Configuration Serial Output Timing Diagram

Figure 28. AS Configuration Serial Input Timing Diagram

¹⁴⁴ AS operating at maximum clock frequency = 133 MHz. The delay is larger when operating at AS clock frequency lower than 133 MHz.

¹⁴⁵

T_{ext_delay} = T_{bd_clk} + T_co + T_{bd_data} + T_add

T_{bd_clk}: Propagation delay for AS_CLK between FPGA and flash device.

T_co: Output hold time and clock low to output valid of flash device. This delay must be used to ensure T_{ext_delay} is within the minimum and maximum specification values.

T_{bd_data}: Propagation delay for AS_DATA bus between FPGA and flash device.

T_add: Propagation delay for active/passive components on AS_DATA interfaces.

Avalon-ST Configuration Timing

Table 93. Avalon-ST Timing Parameters for ×8, ×16, and ×32 Configurations in Intel^® Stratix^® 10 Devices
Symbol	Description	Minimum	Maximum	Unit
t_ACLKH	`AVST_CLK` high time	3.6	—	ns
t_ACLKL	`AVST_CLK` low time	3.6	—	ns
t_ACLKP	`AVST_CLK` period	8	—	ns
t_ADSU ¹⁴⁶	`AVST_DATA` setup time before rising edge of `AVST_CLK`	5.5	—	ns
t_ADH ¹⁴⁶	`AVST_DATA` hold time after rising edge of `AVST_CLK`	0	—	ns
t_AVSU	`AVST_VALID` setup time before rising edge of `AVST_CLK`	5.5	—	ns
t_AVDH	`AVST_VALID` hold time after rising edge of `AVST_CLK`	0	—	ns

Figure 29. Avalon-ST Configuration Timing Diagram

¹⁴⁶ Data sampled by the FPGA (sink) at the next rising clock edge.

SD/MMC Configuration Timing

Table 94. SD/MMC Timing Parameters for Intel^® Stratix^® 10 Devices
For SD or MMC cards, a level shifter/translator is required to shift down the voltage from 3.0 V to 1.8 V when interfacing the SD/MMC card I/Os with FPGA SDM I/O.

The SD/MMC configuration scheme will be available in a future release of the Intel^® Quartus^® Prime software.
Symbol	Description	Minimum	Typical	Maximum	Unit
t_SDCLKP	`SDMMC_CFG_CCLK` clock period (Identification mode)	—	2,500	—	ns
	`SDMMC_CFG_CCLK` clock period (Standard SD mode)	—	40	—	ns
	`SDMMC_CFG_CCLK` clock period (High-speed SD mode)	—	20	—	ns
t_DUTYCYCLE	`SDMMC_CFG_CCLK` duty cycle	45	50	55	%
t_d	`SDMMC_CFG_CMD`/`SDMMC_CFG_DATA` output delay	7.3	—	10.1	ns
t_SU	`SDMMC_CFG_CMD`/`SDMMC_CFG_DATA` input setup	5	—	—	ns
t_H	`SDMMC_CFG_CMD`/`SDMMC_CFG_DATA` input hold	1.5	—	—	ns

Figure 30. SD/MMC Timing Diagram

Configuration Bit Stream Sizes

Table 95. Configuration Bit Stream Sizes for Intel^® Stratix^® 10 DevicesThis table shows the estimated configuration bit stream sizes of the EPCQ-L serial configuration device or external flash size before design compilation. The sizes are for compressed bit stream. The actual sizes may vary based on your design. The actual sizes may be equal or smaller than the bit stream sizes in this table.
Variant	Product Line	Compressed Configuration Bit Stream Size (Mbits)	IOCSR Bit Stream Size (Mbits)
Intel^® Stratix^® 10 GX, SX, TX, and MX	GX 400, GX 650, SX 400, SX 650	100