仅对英特尔可见 — GUID: oxk1484328110710
Ixiasoft
2.3.1. 协议预置
2.3.2. GXT通道
2.3.3. 常规参数和数据通道参数
2.3.4. PMA参数
2.3.5. PCS-Core接口参数
2.3.6. 模拟PMA设置参数
2.3.7. Enhanced PCS参数
2.3.8. Standard PCS参数
2.3.9. PCS Direct数据通路参数
2.3.10. 动态重配置参数
2.3.11. 生成选项参数
2.3.12. PMA,校准和复位端口
2.3.13. PCS-Core接口端口
2.3.14. 增强PCS端口
2.3.15. 标准PCS端口
2.3.16. 收发器PHY PCS-to-Core接口参考端口映射
2.3.17. IP Core文件位置
2.5.1.1. PIPE的收发器通道数据通路
2.5.1.2. 支持的PIPE特性
2.5.1.3. 如何连接PIPE Gen1、Gen2和Gen3模式的TX PLL
2.5.1.4. 如何在 Intel® Stratix® 10收发器中实现PCI Express (PIPE)
2.5.1.5. PIPE的Native PHY IP Core参数设置
2.5.1.6. 用于PIPE的fPLL IP Core参数设置
2.5.1.7. 用于PIPE的ATX PLL IP Core参数设置
2.5.1.8. 用于PIPE的Native PHY IP Core端口
2.5.1.9. 用于PIPE的fPLL端口
2.5.1.10. 用于PIPE的ATX PLL端口
2.5.1.11. 到TX去加重的预置映射(Preset Mappings to TX De-emphasis)
2.5.1.12. 如何对PIPE配置布局通道
2.5.1.13. Gen3的链路均衡
2.5.1.14. 时序收敛建议
6.1. 重配置通道和PLL模块
6.2. 与重配置接口进行交互
6.3. 多个重配置设置文件(Multiple Reconfiguration Profiles)
6.4. 仲裁(arbitration)
6.5. 动态重配置的建议
6.6. 执行动态重配置的步骤
6.7. 直接重配置流程
6.8. Native PHY IP或PLL IP Core指导的重配置流程
6.9. 特殊情况的重配置流程
6.10. 更改模拟PMA设置
6.11. 端口和参数
6.12. 多个IP模块之间的动态重配置接口合并
6.13. 嵌入式调试功能
6.14. 时序收敛建议
6.15. 不支持的功能
6.16. 收发器寄存器映射
6.17. 重配置接口和动态重配置修订历史
7.5.1. 重新校准一个双工通道(PMA TX和PMA RX)
7.5.2. 仅在双工通道中重新校准PMA RX
7.5.3. 仅在双工通道中重新校准PMA TX
7.5.4. 在没有合并到同一物理通道的单工TX的情况下重新校准PMA单工RX
7.5.5. 在没有合并到同一物理通道的单工RX的情况下重新校准PMA单工TX
7.5.6. 仅重新校准单工TX合并的物理通道中的PMA单工RX
7.5.7. 仅重新校准单工RX合并的物理通道中的PMA单工TX
7.5.8. 重新校准fPLL
7.5.9. 重新校准ATX PLL
7.5.10. 当CMU PLL用作TX PLL时,重新校准CMU PLL
仅对英特尔可见 — GUID: oxk1484328110710
Ixiasoft
2.5.1.7. 用于PIPE的ATX PLL IP Core参数设置
本节包含此协议的建议参数值。请参考Using the Intel® Stratix® 10 L-Tile/H-Tile Transceiver Native PHY IP Core来了解参数值的完整范围。
参数 | Gen1 PIPE | Gen2 PIPE | Gen3 PIPE |
---|---|---|---|
Message level for rule violations | Error | Error | Error |
Protocol mode | PCIe Gen 1 | PCIe G2 | PCIe G3 |
Bandwidth | Low, medium, high | Low, medium, high | Low, medium, high |
Number of PLL reference clocks | 1 | 1 | 1 |
Selected reference clock source | 0 | 0 | 0 |
VCCR_GXB and VCCT_GXB supply voltage for the transceiver | 1_0V, 1_1V | 1_0V, 1_1V | 1_0V, 1_1V |
Primary PLL clock output buffer | GX clock output buffer | GX clock output buffer | GX clock output buffer |
Enable GX clock output port (tx_serial_clk) | On | On | On |
Enable GXT clock output port to above ATX PLL (gxt_output_to_abv_atx) | Off | Off | Off |
Enable GXT clock output port to below ATX PLL (gxt_output_to_blw_atx) | Off | Off | Off |
Enable GXT local clock output porttx_serial_clk_gxt) | Off | Off | Off |
Enable GXT clock input port from above ATX PLL (gxt_input_from_abv_atx) | Off | Off | Off |
Enable GXT clock input port from below ATX PLL (gxt_input_from_blw_atx) | Off | Off | Off |
Enable PCIe clock output port | On | On | Off 37 |
Enable ATX to fPLL cascade clock output port | N/A | N/A | N/A |
Enable GXT clock buffer to above ATX PLL | Off | Off | Off |
Enable GXT clock buffer to below ATX PLL | Off | Off | Off |
GXT output clock source | Disabled | Disabled | Disabled |
PLL output frequency | 1250MHz | 2500MHz | 4000MHz |
PLL output datarate | 2500Mbps | 5000Mbps | 8000Mbps |
PLL auto mode reference clock frequency(integer) | 100MHz | 100MHz | 100MHz |
Configure counters manually | Off | Off | Off |
Multiply factor (M-counter) | N/A | N/A | N/A |
Divide factor (N-counter) | N/A | N/A | N/A |
Divide factor (L-counter) | N/A | N/A | N/A |
Include Master clock generation block | x1 — Off x2, x4, x8, x16 — On |
x1 — Off x2, x4, x8, x16 — On |
x1 — Off x2, x4, x8, x16 — On |
Clock division factor | 1 | 1 | 1 |
Enable x24 non-bonded high – speed clock output port | Off | Off | Off |
Enable PCIe clock switch interface | Off | Off | On |
Enable mcgb_rst and mcgb_rst_stat ports | Off | Off | Off |
Number of auxiliary MCGB clock input ports | 0 | 0 | x1 — N/A x2, x4, x8, x16 — 1 |
MCGB input clock frequency | 1250MHz | 2500MHz | 4000MHz |
MCGB output data rate | 2500Mbps | 5000Mbps | 8000Mbps |
Enable bonding clock output ports | x1 — Off x2, x4, x8, x16 — On |
x1 — Off x2, x4, x8, x16 — On |
x1 — Off x2, x4, x8, x16 — On |
PMA interface width | 10 | 10 | 32 |
Enable Dynamic reconfiguration | On / Off | On / Off | On / Off |
Enable Native PHY debug master endpoint | On / Off | On / Off | On / Off |
Separate reconfig_waitrequest from the status of AVMM arbitration with PreSICE | Off | Off | Off |
Enable capability registers | On / Off | On / Off | On / Off |
Set user – defined IP identifier | <IP identifier> | <IP identifier> | <IP identifier> |
Enable control and status registers | On / Off | On / Off | On / Off |
Configuration file prefix | <File prefix> | <File prefix> | <File prefix> |
Generate SystemVerilog package file | On / Off | On / Off | On / Off |
Generate C header file | On / Off | On / Off | On / Off |
Generate MIF (Memory Initialization file) | On / Off | On / Off | On / Off |
Enable multiple reconfiguration profiles | Off | Off | Off |
Enable embedded reconfiguration streamer | Off | Off | Off |
Generate reduced reconfiguration files | Off | Off | Off |
37 Use the pll_pcie_clk output port from the fPLL to drive the hclk.