Intel® Arria® 10 Avalon® Streaming with SR-IOV IP for PCIe* User Guide

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ID 683686
Date 1/11/2022
Public
Document Table of Contents

6.16.12. TPH Requester Control Register

Table 91.  TPH Requester Control Register - 0x308

Bits

Register Description

Default Value

Access

[31:9]

Reserved.

0

RO

[8] TPH Requester Enable: When set to 1, the Function can generate requests with Transaction Processing Hints. 0

RW

[7:3] Reserved. 0

RO

[2:0] ST Mode. The following encodings are defined:
  • 3b'000: No Steering Tag Mode
  • 3'b001: Interrupt Vector Mode
  • 3'b010: Device-specific mode
  • 3'b011 - 3'b111: Reserved
0

RW

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