Stratix V Avalon-ST Interface with SR-IOV PCIe Solutions: User Guide

ID 683488
Date 5/02/2016
Document Table of Contents

1.7. Performance and Resource Utilization

Because the PCIe protocol stack is implemented in hardened logic, it uses no core device resources (no ALMs and no embedded memory).

The SR-IOV Bridge is implemented is soft logic, requiring FPGA fabric resources. The following table shows the typical device resource utilization for selected configurations using the current version of the Quartus® Prime software. With the exception of M20K memory blocks, the numbers of ALMs and logic registers are rounded up to the nearest 50.

Table 6.  Performance and Resource Utilization Stratix® V Avalon-ST with SR-IOV
Number of PFs and VFs


M20K Memory Blocks

Logic Registers

2 PFs




1 PF, 4 VFs




1 PF, 32 VFs 3250 14 5950
2 PFs, 64 VFs 3650 14 6550
2 PFs, 128 VFs 6450 14 9900
Note: Soft calibration of the transceiver module requires additional logic. The amount of logic required depends upon the configuration.

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