Stratix V Avalon-ST Interface with SR-IOV PCIe Solutions: User Guide

ID 683488
Date 5/02/2016
Public
Document Table of Contents

4.14.2. Channel Placement in Arria V GZ and Stratix V GX/GT/GS Devices

Figure 24.  Arria V GZ and Stratix V GX/GT/GS Gen1 and Gen2 Channel Placement Using the CMU PLLIn the following figures the channels shaded in blue provide the transmit CMU PLL generating the high-speed serial clock.
Figure 25. Arria V GZ and Stratix V GX/GT/GS Gen3 Channel Placement Using the CMU and ATX PLLsGen3 requires two PLLs to facilitate rate switching between the Gen1, Gen2, and Gen3 data rates. Channels shaded in blue provide the transmit CMU PLL generating the high-speed serial clock. The ATX PLL shaded in blue is the ATX PLL used in these configurations.
Figure 26. Arria V GZ and Stratix V GX/GT/GS Gen1 and Gen2 Channel Placement Using the ATX PLLSelecting the ATX PLL has the following advantages over selecting the CMU PLL:
  • The ATX PLL saves one channel in Gen1 and Gen2 ×1, ×2, and ×4 configurations.
  • The ATX PLL has better jitter performance than the CMU PLL.
Note: You must use the soft reset controller when you select the ATX PLL and you cannot use CvP.

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