Stratix V Avalon-ST Interface with SR-IOV PCIe Solutions: User Guide

ID 683488
Date 5/02/2016
Public
Document Table of Contents

4.12. Reset, Status, and Link Training Signals

Table 33.  Reset Signals

Signal

Direction

Description

npor

Input

Active low reset signal. In the Intel hardware example designs, npor is the OR of pin_perst and local_rstn coming from the software Application Layer. If you do not drive a soft reset signal from the Application Layer, this signal must be derived from pin_perst. You cannot disable this signal. Resets the entire Stratix V Hard IP for PCI Express IP Core and transceiver. Asynchronous.

When CvP is enabled, an embedded hard reset controller triggers after the internal status signal indicates that the periphery image is loaded. This embedded reset does not trigger off of pin_perst.

In systems that use the hard reset controller, this signal is edge, not level sensitive; consequently, you cannot use a low value on this signal to hold custom logic in reset. For more information about the hard and soft reset controllers, refer to Reset.

pin_perst

Input

Active low reset from the PCIe reset pin of the device.

It resets the datapath and control registers. This signal is required for Configuration via Protocol (CvP). For more information about CvP refer to Configuration via Protocol (CvP).

Stratix V devices have up to 4 instances of the Hard IP for PCI Express. Each instance has its own pin_perst signal.

Every Stratix V device has 4 nPERST pins, even devices with fewer than 4 instances of the Hard IP for PCI Express. You must connect the pin_perst of each Hard IP instance to the corresponding nPERST pin of the device. These pins have the following locations:

  • nPERSTL0: bottom left Hard IP and CvP blocks
  • nPERSTL1: top left Hard IP block
  • nPERSTR0: bottom right Hard IP block
  • nPERSTR1: top right Hard IP block

For example, if you are using the Hard IP instance in the bottom left corner of the device, you must connect pin_perst to nPERSL0.

For maximum use of the Stratix V device, Intel recommends that you use the bottom left Hard IP first. This is the only location that supports CvP over a PCIe link.

Refer to the appropriate Stratix V device pinout for correct pin assignment for more detailed information about these pins. The PCI Express Card Electromechanical Specification 2.0 specifies this pin to require 3.3 V. You can drive this 3.3V signal to the nPERST* even if the VVCCPGM of the bank is not 3.3V if the following 2 conditions are met:

  • The input signal meets the VIH and VIL specification for LVTTL.
  • The input signal meets the overshoot specification for 100°C operation as specified by the “Maximum Allowed Overshoot and Undershoot Voltage” section in volume 3 of the Stratix V Device Handbook.

Figure 22. Reset and Link Training Timing Relationships

The following figure illustrates the timing relationship between npor and the LTSSM L0 state.

Table 34.  Hard IP Reset Status Signals

Signal

Direction

Description

pld_clk_inuse

Output

When asserted, indicates that the Hard IP Transaction Layer is using the pld_clk as its clock and is ready for operation with the Application Layer. For reliable operation, hold the Application Layer in reset until pld_clk_inuse is asserted.

pld_core_ready

Input

When asserted, indicates that the Application Layer is ready for operation and is providing a stable clock to the pld_clk input. If the coreclkout_hip Hard IP output clock is sourcing the pld_clk Hard IP input, this input can be connected to the serdes_pll_locked output.

reset_status

Output

Active high reset status signal. When asserted, this signal indicates that the Hard IP clock is in reset. The reset_status signal is synchronous to the pld_clk clock and is deasserted only when the npor is deasserted and the Hard IP for PCI Express is not in reset (reset_status_hip = 0). You should use reset_status to drive the reset of your Application Layer. It resets the Hard IP at power-up, for hot reset and link down events.

serdes_pll_locked

Output

When asserted, indicates that the PLL that generates the coreclkout_hip clock signal is locked. In pipe simulation mode this signal is always asserted.

testin_zero

Output

When asserted, indicates accelerated initialization for simulation is active.
Table 35.  Status and Link Training SignalsThe following table describes additional signals related to the reset function for the including the ltsssm_state[4:0] bus that indicates the current link training state. These signals are not top-level signals of the Stratix V Hard IP for PCI Express IP Core with SR-IOV. They are listed here to assist in debugging link training issues.

Signal

Direction

Description

cfg_par_err

Output

Indicates that a parity error in a TLP routed to the internal Configuration Space. You must reset the Hard IP if this error occurs.

derr_cor_ext_rcv

Output

Indicates a corrected error in the RX buffer. This signal is for debug only. It is not valid until the RX buffer is filled with data. This is a pulse, not a level, signal. Internally, the pulse is generated with the 500 MHz clock. A pulse extender extends the signal so that the FPGA fabric running at 250 MHz can capture it. Because the error was corrected by the IP core, no Application Layer intervention is required. 4

derr_cor_ext_rpl

Output

Indicates a corrected ECC error in the retry buffer. This signal is for debug only. Because the error was corrected by the IP core, no Application Layer intervention is required. 4 (4)

derr_rpl

Output

Indicates an uncorrectable error in the retry buffer. This signal is for debug only. (4)

dlup

Output

When asserted, indicates that the Hard IP block is in the Data Link Control and Management State Machine (DLCMSM) DL_Up state.

dlup_exit

Output

This signal is asserted low for one pld_clk cycle when the IP core exits the DLCMSM DL_Up state, indicating that the Data Link Layer has lost communication with the other end of the PCIe link and left the Up state. When this pulse is asserted, the Application Layer should generate an internal reset signal that is asserted for at least 32 cycles.

ev128ns

Output

Asserted every 128 ns to create a time base aligned activity.

ev1us

Output

Asserted every 1 µs to create a time base aligned activity.

hotrst_exit

Output

Hot reset exit. This signal is asserted for 1 clock cycle when the LTSSM exits the hot reset state. This signal should cause the Application Layer to be reset. This signal is active low. When this pulse is asserted, the Application Layer should generate an internal reset signal that is asserted for at least 32 cycles.

int_status[3:0]

Output

These signals drive legacy interrupts to the Application Layer as follows:

  • int_status[0]: interrupt signal A
  • int_status[1]: interrupt signal B
  • int_status[2]: interrupt signal C
  • int_status[3]: interrupt signal D
l2_exit

Output

L2 exit. This signal is active low and otherwise remains high. It is asserted for one cycle (changing value from 1 to 0 and back to 1) after the LTSSM transitions from l2.idle to detect. When this pulse is asserted, the Application Layer should generate an internal reset signal that is asserted for at least 32 cycles.

lane_act[3:0]

Output

Lane Active Mode: This signal indicates the number of lanes that configured during link training. The following encodings are defined:

  • 4’b0001: 1 lane
  • 4’b0010: 2 lanes
  • 4’b0100: 4 lanes
  • 4’b1000: 8 lanes
ltssmstate[4:0]

Output

LTSSM state: The LTSSM state machine encoding defines the following states:

  • 00000: Detect.Quiet
  • 00001: Detect.Active
  • 00010: Polling.Active
  • 00011: Polling.Compliance
  • 00100: Polling.Configuration
  • 00101: Polling.Speed
  • 00110: config.Linkwidthstart
  • 00111: Config.Linkaccept
  • 01000: Config.Lanenumaccept
  • 01001: Config.Lanenumwait
  • 01010: Config.Complete
  • 01011: Config.Idle
  • 01100: Recovery.Rcvlock
  • 01101: Recovery.Rcvconfig
  • 01110: Recovery.Idle
  • 01111: L0
  • 10000: Disable
  • 10001: Loopback.Entry
  • 10010: Loopback.Active
  • 10011: Loopback.Exit
  • 10100: Hot.Reset
  • 10101: L0s
  • 11001: L2.transmit.Wake
  • 11010: Recovery.Speed
  • 11011: Recovery.Equalization, Phase 0
  • 11100: Recovery.Equalization, Phase 1
  • 11101: Recovery.Equalization, Phase 2
  • 11110: Recovery.Equalization, Phase 3
  • 11111: Recovery.Equalization, Done
rx_par_err

Output

When asserted for a single cycle, indicates that a parity error was detected in a TLP at the input of the RX buffer. The SR-IOV bridge drives this signal to the Application Layer without taking any action. If this error occurs, you must reset the Hard IP because parity errors can leave the Hard IP in an unknown state.

tx_par_err[1:0]

Output

When asserted for a single cycle, indicates a parity error during TX TLP transmission. The SR-IOV bridge drives this signal to the Application Layer without taking any action. The following encodings are defined:

  • 2’b10: A parity error was detected by the TX Transaction Layer.
  • 2’b01: Some time later, the parity error is detected by the TX Data Link Layer which drives 2’b01 to indicate the error. Intel recommends resetting the Stratix V Hard IP for PCI Express when this error is detected. Contact Intel if resetting becomes unworkable.
Note: Not all simulation models assert the Transaction Layer error bit in conjunction with the Data Link Layer error bit.
ko_cpl_spc_data[11:0]

Output

The Application Layer can use this signal to build circuitry to prevent RX buffer overflow for completion data. Endpoints must advertise infinite space for completion data; however, RX buffer space is finite. ko_cpl_spc_data is a static signal that reflects the total number of 16 byte completion data units that can be stored in the completion RX buffer.

ko_cpl_spc_header]7:0]

Output

The Application Layer can use this signal to build circuitry to prevent RX buffer overflow for completion headers. Endpoints must advertise infinite space for completion headers; however, RX buffer space is finite. ko_cpl_spc_header is a static signal that indicates the total number of completion headers that can be stored in the RX buffer.

rxfc_cplbuf_ovf Output When asserted, indicates RX Posted Completion buffer overflow.
4 Debug signals are not rigorously verified and should only be used to observe behavior. Debug signals should not be used to drive logic custom logic.

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