Stratix V Avalon-ST Interface with SR-IOV PCIe Solutions: User Guide

ID 683488
Date 5/02/2016
Document Table of Contents

10. Transceiver PHY IP Reconfiguration

As silicon progresses towards smaller process nodes, circuit performance is affected by variations due to process, voltage, and temperature (PVT). Consequently, Gen3 designs require offset cancellation and adaptive equalization (AEQ) to ensure correct operation. Altera’s Qsys example designs all include Transceiver Reconfiguration Controller and Altera PCIe Reconfig Driver IP cores that automatically perform these functions during the LTSSM equalization states.

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