Stratix V Avalon-ST Interface with SR-IOV PCIe Solutions: User Guide

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ID 683488
Date 5/02/2016
Public
Document Table of Contents
Document Table of Contents x
1. Datasheet 2. Getting Started with the SR-IOV DMA Example Design 3. Parameter Settings 4. Interfaces and Signal Descriptions 5. Registers 6. Programming and Testing SR-IOV Bridge MSI Interrupts 7. Error Handling 8. IP Core Architecture 9. Design Implementation 10. Transceiver PHY IP Reconfiguration 11. Debugging A. Frequently Asked Questions for PCI Express B. Transaction Layer Packet (TLP) Header Formats C. Stratix V Avalon-ST with SR-IOV Interface for PCIe Solutions User Guide Archive 12. Document Revision History
1. Datasheet x
1.1. Stratix® V Avalon-ST Interface with SR-IOV for PCIe Datasheet 1.2. Release Information 1.3. Device Family Support 1.4. Design Examples for SR-IOV 1.5. Debug Features 1.6. IP Core Verification 1.7. Performance and Resource Utilization 1.8. Recommended Speed Grades for SR-IOV Interface 1.9. Creating a Design for PCI Express
1.1. Stratix® V Avalon-ST Interface with SR-IOV for PCIe Datasheet x
1.1.1. SR-IOV Features
1.6. IP Core Verification x
1.6.1. Compatibility Testing Environment
2. Getting Started with the SR-IOV DMA Example Design x
2.1. Generating the Example Design Testbench 2.2. Understanding the Generated Files and Directories 2.3. Simulating the SR-IOV Example Design 2.4. Running a Gate-Level Simulation 2.5. Understanding the DMA Functionality 2.6. Compiling the Example Design with the Quartus® Prime Software 2.7. Using the IP Catalog To Generate Your Stratix V Hard IP for PCI Express as a Separate Component
3. Parameter Settings x
3.1. System Settings 3.2. SR-IOV System Settings 3.3. Base Address Register (BAR) Settings 3.4. SR-IOV Device Identification Registers 3.5. Interrupt Capabilities 3.6. PCI Express and PCI Capabilities Parameters 3.7. PHY Characteristics 3.8. Simulation Options
3.6. PCI Express and PCI Capabilities Parameters x
3.6.1. Device Capabilities 3.6.2. Error Reporting 3.6.3. Link Capabilities 3.6.4. Slot Capabilities 3.6.5. Power Management
4. Interfaces and Signal Descriptions x
4.1. Avalon-ST TX Interface 4.2. Component-Specific Avalon-ST Interface Signals 4.3. Avalon-ST RX Interface 4.4. BAR Hit Signals 4.5. Configuration Status Interface 4.6. Clock Signals 4.7. Function-Level Reset Interface 4.8. Interrupt Interface 4.9. Configuration Extension Bus (CEB) Interface 4.10. Implementing MSI-X Interrupts 4.11. Local Management Interface (LMI) Signals 4.12. Reset, Status, and Link Training Signals 4.13. Transceiver Reconfiguration 4.14. Serial Data Signals 4.15. Test Signals 4.16. PIPE Interface Signals
4.9. Configuration Extension Bus (CEB) Interface x
4.9.1. Vital Product Data (VPD) Capability
4.9.1. Vital Product Data (VPD) Capability x
4.9.1.1. Determine the Pointer Address of an External Capability Register 4.9.1.2. VPD Capability Implementation
4.14. Serial Data Signals x
4.14.1. Physical Layout of Hard IP In Stratix V Devices 4.14.2. Channel Placement in Arria V GZ and Stratix V GX/GT/GS Devices
5. Registers x
5.1. Correspondence between Configuration Space Registers and the PCIe Specification 5.2. PCI and PCI Express Configuration Space Registers 5.3. MSI Registers 5.4. MSI-X Capability Structure 5.5. Power Management Capability Structure 5.6. PCI Express Capability Structure 5.7. Advanced Error Reporting (AER) Enhanced Capability Header Register 5.8. Uncorrectable Error Status Register 5.9. Uncorrectable Error Mask Register 5.10. Uncorrectable Error Severity Register 5.11. Correctable Error Status Register 5.12. Correctable Error Mask Register 5.13. Advanced Error Capabilities and Control Register 5.14. Header Log Registers 0-3 5.15. SR-IOV Virtualization Extended Capabilities Registers 5.16. Virtual Function Registers
5.2. PCI and PCI Express Configuration Space Registers x
5.2.1. Type 0 Configuration Space Registers 5.2.2. PCI and PCI Express Configuration Space Register Content 5.2.3. Interrupt Line and Interrupt Pin Register
5.15. SR-IOV Virtualization Extended Capabilities Registers x
5.15.1. SR-IOV Virtualization Extended Capabilities Registers Address Map 5.15.2. ARI Enhanced Capability Header 5.15.3. SR-IOV Enhanced Capability Registers 5.15.4. Initial VFs and Total VFs Registers 5.15.5. VF Device ID Register 5.15.6. Page Size Registers 5.15.7. VF Base Address Registers (BARs) 0-5 5.15.8. Secondary PCI Express Extended Capability Header 5.15.9. Lane Status Registers
6. Programming and Testing SR-IOV Bridge MSI Interrupts x
6.1. Setting Up and Verifying MSI Interrupts 6.2. Masking MSI Interrupts 6.3. Dropping a Pending MSI Interrupt
7. Error Handling x
7.1. Physical Layer Errors 7.2. Data Link Layer Errors 7.3. Transaction Layer Errors 7.4. Error Reporting and Data Poisoning 7.5. Uncorrectable and Correctable Error Status Bits
8. IP Core Architecture x
8.1. Data Link Layer 8.2. Physical Layer 8.3. Top-Level Interfaces 8.4. Physical and Virtual Function Address Assignments 8.5. Stratix V Hard IP for PCI Express with Single-Root I/O Virtualization (SR-IOV)
8.3. Top-Level Interfaces x
8.3.1. Avalon-ST Interface 8.3.2. Clocks and Reset 8.3.3. Transceiver Reconfiguration 8.3.4. Interrupts 8.3.5. PIPE
9. Design Implementation x
9.1. Making Analog QSF Assignments Using the Assignment Editor 9.2. Making Pin Assignments to Assign I/O Standard to Serial Data Pins 9.3. Recommended Reset Sequence to Avoid Link Training Issues 9.4. SDC Timing Constraints
10. Transceiver PHY IP Reconfiguration x
10.1. Connecting the Transceiver Reconfiguration Controller IP Core 10.2. Transceiver Reconfiguration Controller Connectivity for Designs Using CvP
11. Debugging x
11.1. Setting Up Simulation 11.2. Hardware Bring-Up Issues 11.3. Link Training 11.4. Use Third-Party PCIe Analyzer 11.5. BIOS Enumeration Issues
11.1. Setting Up Simulation x
11.1.1. Changing Between Serial and PIPE Simulation 11.1.2. Using the PIPE Interface for Gen1 and Gen2 Variants 11.1.3. Viewing the Important PIPE Interface Signals 11.1.4. Disabling the Scrambler for Gen1 and Gen2 Simulations 11.1.5. Disabling 8B/10B Encoding and Decoding for Gen1 and Gen2 Simulations 11.1.6. Changing between the Hard and Soft Reset Controller
11.3. Link Training x
11.3.1. Debugging Link that Fails To Reach L0
B. Transaction Layer Packet (TLP) Header Formats x
B.1. TLP Packet Formats without Data Payload B.2. TLP Packet Formats with Data Payload
12. Document Revision History x
12.1. Document Revision History for the Intel® Arria® 10 Avalon® Streaming with SR-IOV IP for PCIe* User Guide
1. Datasheet
2. Getting Started with the SR-IOV DMA Example Design
3. Parameter Settings
4. Interfaces and Signal Descriptions
5. Registers
6. Programming and Testing SR-IOV Bridge MSI Interrupts
7. Error Handling
8. IP Core Architecture
9. Design Implementation
10. Transceiver PHY IP Reconfiguration
11. Debugging
A. Frequently Asked Questions for PCI Express
B. Transaction Layer Packet (TLP) Header Formats
C. Stratix V Avalon-ST with SR-IOV Interface for PCIe Solutions User Guide Archive
12. Document Revision History

5.6. PCI Express Capability Structure

Figure 31. PCI Express Capability Structure - Byte Address Offsets and LayoutIn the following table showing the PCI Express Capability Structure, registers that are not applicable to a device are reserved.
Table 52.  PCI Express Capability Register - 0x080
Bits Description Default Value Access
[31:19] Reserved 0 RO
[18:16] Version ID: Version of Power Management Capability. 0x3 RO
[15:8] Next Capability Pointer: Points to the PCI Express Capability. 0x80 RO
[7:0] Capability ID assigned by PCI-SIG. 0x01 RO
Table 53.   PCI Express Device Capabilities Register -0x084
Bits Description Default Value Access
[2:0] Maximum Payload Size supported by the Function. Can be configured as 000 (128 bytes) or 001 (256 bytes) Set in Platform Designer RO
[4:3] Reserved 0 RO
[5] Extended tags supported Set in Platform Designer RO
[8:6] Acceptable L0S latency Set in Platform Designer RO
[11:9] Acceptable L1 latency Set in Platform Designer RO
[14:12] Reserved 0 RO
[15] Role-Based error reporting supported 1 RO
[17:16] Reserved 0 RO
[27:18] Captured Slot Power Limit Value and Scale: Not implemented 0 RO
[28] FLR Capable. Indicates that the device has FLR capability Set in Platform Designer RO
[31:29 ] Reserved 0 RO
Table 54.   PCI Express Device Control and Status Register - 0x088
Bits Description Default Value Access
[0] Enable Correctable Error Reporting. 0 RW
[1] Enable Non-Fatal Error Reporting. 0 RW
[2] Enable Fatal Error Reporting. 0 RW
[3] Enable Unsupported Request (UR) Reporting. 0 RW
[4] Enable Relaxed Ordering. Set in Platform Designer RW
[7:5] Maximum Payload Size. 0 (128 bytes) RW
[8] Extended Tag Field Enable. 0 RW
[10:9] Reserved. 0 RO
[11] Enable No-Snoop. 1 RW
[14:12] Maximum Read Request Size. 2 (512 bytes) RW
[15] Function-Level Reset. Writing a 1 generates a Function-Level Reset for this Function if the FLR Capable bit of the Device Capabilities Register is set. This bit always reads as 0. 0 RW
[16] Correctable Error detected. 0 RW1C
[17] Non-Fatal Error detected. 0 RW1C
[18] Fatal Error detected. 0 RW1C
[19] Unsupported Request detected. 0 RW1C
[20] Reserved. 0 RO
[21] Transaction Pending: Indicates that a Non- Posted request issued by this Function is still pending. 0 RO
[31:22] Reserved. 0 RO
Table 55.  Link Capabilities Register - 0x08C
Bits Description Default Value Access
[3:0] Maximum Link Speed 1: 2.5 GT/s

2: 5.0 GT/s

3: 8.0 GT/s

RO
[9:4] Maximum Link Width 1, 2, 4 or 8 RO
[10] ASPM Support for L0S state Set in Platform Designer RO
[11] ASPM Support for L1 state Set in Platform Designer RO
[14:12] L0S Exit Latency Set in Platform Designer, 0x6 RO
[17:15] L1 Exit Latency Set in Platform Designer, 0x0 RO
[21:18] Reserved 0 RO
[22] ASPM Optionality Compliance 1 RO
[31:23] Reserved 0 RO
Table 56.   Link Control and Status Register - 0x090
Bits Description Default Value Access
[1:0] ASPM Control 0 RW
[2] Reserved 0 R O
[3] Read Completion Boundary 0 RW
[5:4] Reserved 0 RO
[6] Common Clock Configuration 0 RW
[7] Extended Synch 0 RW
[15:8] Reserved 0 RO
[19:16] Negotiated Link Speed 0 RO
[25:20] Negotiated Link Width 0 RO
[27:26] Reserved 0 RO
[28] Slot Clock Configuration Set in Platform Designer RO
[31:29] Reserved 0 RO
Table 57.   PCI Express Device Capabilities 2 Register - 0x0A4
Bits Description Default Value Access
[3:0] Completion Timeout ranges Set in Platform Designer RO
[4] Completion Timeout disable supported Set in Platform Designer RO
[31:5] Reserved 0 RO
Table 58.   PCI Express Device Control 2 and Status 2 Register - 0x0A8
Bits Description Default Value Access
[3:0] Completion Timeout value 0xF RW
[4] Completion Timeout disable 1 RW
[31:5] Reserved 0 RO
Table 59.   Link Capabilities 2 Register - 0x0AC
Bits Description Default Value Access
[0] Reserved 0 RO
[3:1] Link speeds supported

1 (2.5 GT/s)

3 (5.0 GT/s)

7 (8.0 GT/s)

Set in Platform Designer 		RO
[31:4] Reserved 0 RO
Table 60.  Link Control 2 and Status 2 Register - 0x0B0
Bits Description Default Value Access
[3:0] Target Link Speed

1: Gen1

2: Gen2

3: Gen3

RWS
[4] Enter Compliance 0 RWS
[5] Hardware Autonomous Speed Disable 0 RW
[6] Selectable De-emphasis 0 RO
[9:7] Transmit Margin 0 RWS
[10] Enter Modified Compliance 0 RWS
[11] Compliance SOS 0 RWS
[15:12] Compliance Preset/De-emphasis 0 RWS
[16] Current De-emphasis Level 0 RO
[17] Equalization Complete 0 RO
[18] Equalization Phase 1 Successful 0 RO
[19] Equalization Phase 2 Successful 0 RO
[20] Equalization Phase 3 Successful 0 RO
[21] Link Equalization Request 0 RW1C
[31:22] Reserved 0 RO
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