Stratix V Avalon-ST Interface with SR-IOV PCIe Solutions: User Guide

ID 683488
Date 5/02/2016
Public
Document Table of Contents

2.7. Using the IP Catalog To Generate Your Stratix V Hard IP for PCI Express as a Separate Component

You can also instantiate the Stratix V Hard IP for PCI Express IP Core as a separate component for integration into your project.

You can use the Quartus® Prime IP Catalog and IP Parameter Editor to select, customize, and generate files representing your custom IP variation. The IP Catalog (Tools > IP Catalog) automatically displays IP cores available for your target device. Double-click any IP core name to launch the parameter editor and generate files representing your IP variation.

For more information about the customizing and generating IP Cores refer to Specifying IP Core Parameters and Options in Introduction to Intel FPGA IP Cores. For more information about upgrading older IP cores to the current release, refer to Upgrading Outdated IP Cores in Introduction to Intel FPGA IP Cores.

Note: Your design must include the Transceiver Reconfiguration Controller IP Core and the Altera PCIe Reconfig Driver. Refer to the figure in the Qsys Design Flow section to learn how to connect this components.

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