Stratix V Avalon-ST Interface with SR-IOV PCIe Solutions: User Guide

ID 683488
Date 5/02/2016
Public
Document Table of Contents

4.9.1.1. Determine the Pointer Address of an External Capability Register

The next pointer field of the last capability structure within the SR-IOV bridge is set by the External Capability Pointer parameter (refer to Table 3.3). Separate parameters are provided for the PCI Compatible region of the physical function (PF) and virtual function (VF) as well as for the PCIe Extended Capability region to point to the next capability in the user logic for the physical function and virtual function.

You can select an address from the available address space. Refer to Table 6.2 to determine the available address space to implement additional capabilities.

Most of the address space of the first 256 registers has been taken up by capabilities present in the SR-IOV bridge when all optional capabilities are enabled. If you wish to implement new capabilities in the first 256 registers, some of the optional capabilities in the SR-IOV bridge may need to be disabled.

The figure below shows the default link list of the PCI Compatible region inside the SR-IOV bridge core. Capabilities like MSI and MSI-X are optional.

The figure below shows the link list when the MSI capability is disabled. The SR-IOV bridge automatically adjusts its next pointer when you disable any of the optional capabilities.

When the MSI capability is disabled, the address space available from 0x50 to 0x64 can now be used to implement user-specific capabilities using the CEB interface. As shown in the figure above, the last capability in the link is the PCI Express Capability Structure. The external capability pointer parameter will set the NxtPtr field of the PCI Express Capability Structure in this case. If you implement an additional capability at “0x54”, it must set the external capability pointer parameter value to “0x54”. This allows the PCI Express Capability Structure to point to “0x54” instead of the “null pointer”. The link list will appear as shown in the figure below.

The reserve configuration register space 0x0B4:0x0FF can be used to implement additional capabilities as well. If the MSI capability is disabled in the SR-IOV bridge, the user capability can start with address 0x50 or address 0xB4. If you implement an additional capability at “0x50”, it must set the external capability pointer parameter value to “0x50”. This allows the PCIE capability to point to “0x50” instead of the “null pointer”. The link list will appear as shown in the figure below.

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