Stratix V Avalon-ST Interface with SR-IOV PCIe Solutions: User Guide

ID 683488
Date 5/02/2016
Public
Document Table of Contents

5.15.3. SR-IOV Enhanced Capability Registers

Table 72.   SR-IOV Extended Capability Header Register - 0x240

Bits

Register Description

Default Value

Access

[15:0]

PCI Express Extended Capability ID

0x0010

RO

[19:16] Capability Version 1

RO

[31:16]
Next capability Pointer: The value depends on data rate. The following values are possible:
  • If PF0 supports the Gen3 data rate: Next Capability = Secondary PCIe (0x300).
  • Else: Next Capability = 0.

Set in Platform Designer

RO

Table 73.  SR-IOV Capabilities Register - 0x244

Bits

Register Description

Default Value

Access

[0]

VF Migration Capable

0

RO

[1] ARI Capable Hierarchy Preserved 1, for the lowest-numbered PF with SR-IOV Capability; 0 for other PFs.

RO

[31:2]

Reserved

0

Default Value

RO

Table 74.  SR-IOV Control and Status Registers - 0x248

Bits

Register Description

Default Value

Access

[0]

VF Enable

0

RW

[1] VF Migration Enable. Not implemented. 0

RO

[2]

VF Migration Interrupt Enable. Not implemented.

0

RO

[3] VF Memory Space Enable 0 RW
[4] ARI Capable Hierarchy 0 RW, for the lowest-numbered PF with SR-IOV Capability; RO for other PFs
[15:5] Reserved 0 RO
[31:16] SR-IOV Status Register. Not implemented 0 RO

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