Stratix V Avalon-ST Interface with SR-IOV PCIe Solutions: User Guide

ID 683488
Date 5/02/2016
Public
Document Table of Contents

5.1. Correspondence between Configuration Space Registers and the PCIe Specification

Table 41.  Configuration Space Registers for a Physical Function

Byte Address

SR-IOV Bridge Configuration Space Register

Corresponding Section in PCIe Specification

0x000:0x03C

PCI Header Type 0 Configuration Registers

Type 0 Configuration Space Header

0x040:0x04C

Reserved

N/A

0x050:0x064

MSI Capability Structure

MSI Capability Structure

0x068:0x070

MSI-X Capability Structure

MSI-X Capability Structure

0x074

Reserved

N/A

0x078:0x07C

Power Management Capability Structure

PCI Power Management Capability Structure

0x080:0x0B0

PCI Express Capability Structure

PCI Express Capability Structure

0x0B4:0x0FF

Reserved

N/A

0x100:0x104

ARI Capability Structure. 5

ARI Capability Structure.

0x140:0x168 - ARI supported

0x100:0x128 - No ARI support

Advanced Error Reporting AER (optional)

Advanced Error Reporting Capability

0x180:0x1BC Single-Root I/O Virtualization (SR-IOV) Capability Structure6 SR-IOV Extended Capability Header in Single Root I/O Virtualization and Sharing Specification, Rev. 1.1
0x200:0x218 Secondary PCIe Extended Capability Structure7 Secondary PCIe Extended Capability
0x288:0xFFF Reserved N/A
5 This capability only exists if ARI is enabled.
6 SR-IOV Capability only exists if you enable SR-IOV support
7 When you enable Gen3, the PF0 configuration space supports the Secondary PCIe Extended Capability Structure

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