Stratix V Avalon-ST Interface with SR-IOV PCIe Solutions: User Guide

ID 683488
Date 5/02/2016
Public
Document Table of Contents

2. Getting Started with the SR-IOV DMA Example Design

The SR-IOV example design consists of an SR-IOV bridge configured for one PF and four VFs. Each VF connects to a read DMA and a write DMA engine. The examples design simulates the Transaction, Data Link, and Physical Layers using the Altera Root Port BFM. It also supports Quartus® Primecompilation.

The SR-IOV Qsys example design includes three Qsys subsystems. The top-level Qsys subsystem comprises the following components:

  • DUT: This is the Stratix V Hard IP for PCI Express with SR-IOV.
  • APPs: This component is a Qsys subsystem that implements a highly efficient DMA engine. Each VF has separate descriptor controllers for read DMA and write DMA descriptors. The read DMA and write DMA routers arbitrate requests from the descriptor controllers. They forward the selected request to the read DMA and write DMA modules. The read DMA transfers large blocks of data from the Avalon-ST (SR-IOV) domain to the Avalon-MM (Qsys). The write DMA Write module transfers large blocks of data from the Avalon-MM domain to the Avalon-ST domain. Refer to the SR-IOV Example Design Block Diagram block diagram below.

    In addition to high performance data transfer, the Read DMA and Write DMA modules ensure that the requests on the PCI link adhere to the PCI Express Base Specification, 3.0. The read and write DMA modules also perform the following functions:

    • Divide the original request into multiple requests to avoid crossing 4KByte boundaries.
    • Divide the original request into multiple requests to ensure that the maximum payload size is equal to or smaller than the maximum payload size for write.
    • Divide the original request into multiple requests to ensure that the maximum read size is equal to or smaller than the maximum read request size.
    • Supports out-of-order completions when the original request is divided into multiple requests to adhere to the maximum payload size.
  • Altera PCIe Reconfig Driver IP Core: This Avalon-MM master drives the Transceiver Reconfiguration Controller.
  • Transceiver Reconfiguration Controller IP Core: The Transceiver Reconfiguration Controller dynamically reconfigures analog settings to improve signal quality. For Gen1 and Gen2 data rates, the Transceiver Reconfiguration performs offset cancellation and PLL calibration. For the Gen3 data rate, the pcie_reconfig_driver_0 performs AEQ through the Transceiver Reconfiguration Controller.
Figure 2. SR-IOV Example Design Block Diagram

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