Stratix V Avalon-ST Interface with SR-IOV PCIe Solutions: User Guide

ID 683488
Date 5/02/2016
Public
Document Table of Contents

2.5. Understanding the DMA Functionality

The following figures illustrate the DMA functionality using numbered steps.

Figure 4. Steps to Fetch Descriptor Table from Host Memory
Fetching the Descriptor Table entries includes the following steps:
  1. The host sets up descriptor controller register table using the RX master interface.
  2. The Descriptor Controller instructs the DMA Read module to fetch the descriptor instruction entries.
  3. The Host returns descriptor instruction entries to the Descriptor Controller.
  4. In response to the Descriptor Controller instruction, the DMA Read drives a Memory Read Request to the Hard IP.
Figure 5. Steps To Perform a DMA Read
The Read DMA operation includes the following steps:
  1. The Descriptor Controller sends read descriptor instruction to initiate a DMA read.
  2. The Descriptor Controller transmits a Memory Read TLP to the host starting at the source address.
  3. The host returns DMA read data on the Avalon-ST interface.
  4. The DMA Read Controller writes data to the destination address in the Application Layer memory.
  5. The DMA Read module reports done status for each descriptor to the Descriptor Controller.
  6. When all descriptors are complete, the Descriptor Controller sets the done bit of the last entry in the descriptor table in host memory. The DMA Read Descriptor Controller sends this update to the TX Slave. The TX Slave drives the update to the Hard IP for PCI Express.
Figure 6. Steps To Perform a Write DMA
The Write DMA operation includes the following steps:
  1. The Descriptor Controller sends write descriptor instruction to initiate a DMA write.
  2. The DMA Write reads data from the Application Layer memory.
  3. Descriptor Controller transmits a Memory Write TLP to the host.
  4. The DMA Write reports status for each descriptor to the Descriptor Controller.
  5. When all descriptors are complete, the Descriptor Controller writes the ID of the last completed descriptor to the EPLAST bit of the descriptor table.

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