Stratix V Avalon-ST Interface with SR-IOV PCIe Solutions: User Guide

ID 683488
Date 5/02/2016
Public
Document Table of Contents

5.3. MSI Registers

Figure 28. MSI Register Byte Address Offsets and Layout
Table 44.  MSI Control Register - 0x050

Bits

Register Description

Default Value

Access

[31:25]

Not implemented

0

RO

[24]

Per-Vector Masking Capable. This bit is hardwired to 1. The design always supports per-vector masking of MSI interrupts.

1

RO

[23]

64-bit Addressing Capable. When set, the device is capable of using 64-bit addresses for MSI interrupts.

Set in Platform Designer

RO

[22:20]

Multiple Message Enable. This field defines the number of interrupt vectors for this function. The following encodings are defined:

  • 3'b000: 1 vector
  • 3'b001: 2 vectors
  • 3'b010: 4 vectors
  • 3'b011: 8 vectors
  • 3'b100: 16 vectors
  • 3'b101: 32 vectors

The Multiple Message Capable field specifies the maximum value allowed.

0

RW

[19:17]

Multiple Message Capable. Defines the maximum number of interrupt vectors the function is capable of supporting. The following encodings are defined:

  • 3'b000: 1 vector
  • 3'b001: 2 vectors
  • 3'b010: 4 vectors
  • 3'b011: 8 vectors
  • 3'b100: 16 vectors
  • 3'b101: 32 vectors

Set inPlatform Designer

RO

[16]

MSI Enable. This bit must be set to enable the MSI interrupt generation.

0

RW

[15:8]

Next Capability Pointer. Points to either MSI-X or Power Management Capability.

0x68 or 0x78

RO

[7:0]

Capability ID. PCI-SIG assigns this value.

0x05

RO

Table 45.  MSI Message Address Registers - 0x054 and 0x058

Bits

Register Description

Default Value

Access

[1:0]

The two least significant bits of the memory address. These are hardwired to 0 to align the memory address on a Dword boundary.

0

RO

[31:2]

Lower address for the MSI interrupt.

0

RW

[31:0]

Upper 32 bits of the 64-bit address to be used for the MSI interrupt. If the 64-bit Addressing Capable bit in the MSI Control register is set to 1, this value is concatenated with the lower 32-bits to form the memory address for the MSI interrupt. When the 64-bit Addressing Capable bit is 0, this register always reads as 0.

0

RW

Table 46.  MSI Message Data 0x058 (32-bit addressing) or 0x05C (64-bit addressing) Register

When 64-bit addressing is supported, this location contains the MSI Data Register. Otherwise, it contains the MSI Mask Register

Bits

Register Description

Default Value

Access

[15:0]

Data for MSI Interrupts generated by this function. This base value is written to Root Port memory to signal an MSI interrupt. When one MSI vector is allowed, this value is used directly. When 2 MSI vectors are allowed, the upper 15 bits are used. And, the least significant bit indicates the interrupt number. When 4 MSI vectors are allowed, the lower 2 bits indicate the interrupt number, and so on.

0

RW

[31:16]

Reserved

0

RO

Table 47.  MSI Mask Register - 0x05C (32-bit addressing) 0x060 (64-bit addressing)

Bits

Register Description

Default Value

Access

31:0

Mask bits for MSI interrupts. The number of implemented bits depends on the number of MSI vectors configured. When one MSI vectors is used , only bit 0 is RW. The other bits read as zeros. When two MSI vectors are used, bits [1:0] are RW, and so on. A one in a bit position masks the corresponding MSI interrupt.

See description

0

Table 48.  Pending Bits for MSI Interrupts Register - 0x060 (32-bit addressing) or 0x064 (64-bit addressing)

Bits

Register Description

Default Value

Access

31:0

Pending bits for MSI interrupts. A 1 in a bit position indicated the corresponding MSI interrupt is pending in the core. The number of implemented bits depends on the number of MSI vectors configured. When 1 MSI vectors is used, only bit 0 is RW. The other bits read as zeros. When 2 MSI vectors are used, bits [1:0] are RW, and so on.

RO

0

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