Stratix V Avalon-ST Interface with SR-IOV PCIe Solutions: User Guide

ID 683488
Date 5/02/2016
Public
Document Table of Contents

4.7. Function-Level Reset Interface

The function-level reset (FLR) interface can reset the individual SR-IOV functions.

Table 27.  Function-Level Reset Interface

Signal

Direction

Description

flr_active_pf[<n>-1:0]

Output

When asserted, indicates the PF FLR field (bit 15) of the Device Control Register is set. When asserted, a PF is being reset. (Bit 0 is for PF0. Bit 1 is for PF1).

The Application Layer must monitor flr_active_pf[<n>-1:0] and clear any pending transactions associated with the function being reset. The Application Layer must then assert flr_completed_pf.

flr_completed_pf[<n>-1:0]

Input

When asserted for one or more cycles, indicates that the Application Layer has completed resetting all the logic associated with the PF. (Bit 0 is for PF0. Bit 1 is for PF1). When flr_active_pf is asserted, the Application Layer must assert flr_completed within 100 microseconds to re-enable the function.

flr_active_vf[<n>-1:0]

Output

Asserting bit <n> indicates a 1 was written into the FLR field (bit 15) of the Device Control Register for VF<n>. When asserted, indicates that VF <n> is being reset. Multiple VFs can be reset simultaneously. Consequently, the Application Layer must monitor each bit of this output port in parallel.

The Application Layer must clear any pending transactions associated with the VF being reset. It must then assert the corresponding bit of flr_completed to signal to indicate it is ready to re-enable the VF.

<n> is the total number of VFs.

flr_completed_vf[<n>-1:0]

Input

Asserting bit <n> for one or more cycles indicates that the Application Layer has completed resetting all the logic associated with VF <n>.

When flr_active_vf<n> is asserted, the Application Layer it must assert the corresponding bit of flr_completed within 100 microseconds to re-enable the VF.

<n> is the total number of VFs.

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