Stratix V Avalon-ST Interface with SR-IOV PCIe Solutions: User Guide

ID 683488
Date 5/02/2016
Public
Document Table of Contents

4.2. Component-Specific Avalon-ST Interface Signals

Table 22.  Component Specific Avalon- ST TX Signals

Signal

Direction

Description

tx_cons_cred_select Input

When 1, the output tx_cred_data* and tx_cred_hdr* signals specify the value of the hard IP internal credits-consumed counter. When 0, tx_cred_data* and tx_cred_hdr* signal specify the limit value.

This signal is present when you turn On Enable credit consumed selection port in the parameter editor .

tx_cred_datafccp[11:0]

Output

Data credit limit for the received FC completions. Each credit is 16 bytes.

tx_cred_datafcnp[11:0]

Output

Data credit limit for the non-posted requests. Each credit is 16 bytes.

tx_cred_datafcp[11:0]

Output

Data credit limit for the FC posted writes. Each credit is 16 bytes.

tx_cred_fchipcons[5:0]

Output

Asserted for 1 cycle each time the Hard IP consumes a credit. These credits are from messages that the Hard IP for PCIe generates for the following reasons:

  • To respond to memory read requests
  • To send error messages

This signal is not asserted when an Application Layer credit is consumed. The Application Layer must keep track of its own consumed credits. To calculate the total credits consumed, the Application Layer must add its own credits consumed to those consumed by the Hard IP for PCIe. The credit signals are valid after dlup (data link up) is asserted.

The 6 bits of this vector correspond to the following 6 types of credit types:

  • [5]: posted headers
  • [4]: posted data
  • [3]: non‑posted header
  • [2]: non‑posted data
  • [1]: completion header
  • [0]: completion data

During a single cycle, the IP core can consume either a single header credit or both a header and a data credit.

tx_cred_fc_infinite[5:0]

Output

When asserted, indicates that the corresponding credit type has infinite credits available and does not need to calculate credit limits. The 6 bits of this vector correspond to the following 6 types of credit types:

  • [5]: posted headers
  • [4]: posted data
  • [3]: non‑posted header
  • [2]: non‑posted data
  • [1]: completion header
  • [0]: completion data
tx_cred_hdrfccp[7:0]

Output

Header credit limit for the FC completions. Each credit is 20 bytes.

tx_cred_hdrfcnp[7:0]

Output

Header limit for the non-posted requests. Each credit is 20 bytes.

tx_cred_hdrfcp[7:0]

Output

Header credit limit for the FC posted writes. Each credit is 20 bytes.

The following table describes the signals that comprise the completion side band signals for the Avalon-ST interface. The Stratix V Hard IP for PCI Express provides a completion error interface that the Application Layer can use to report errors, such as programming model errors. When the Application Layer detects an error, it can assert the appropriate cpl_err bit to indicate what kind of error to log. If separate requests result in two errors, both are logged. The Hard IP sets the appropriate status bits for the errors in the Configuration Space. It also automatically sends error messages in accordance with the PCI Express Base Specification. Note that the Application Layer is responsible for sending the completion with the appropriate completion status value for non-posted requests. Refer to Error Handling for information on errors that are automatically detected and handled by the Hard IP.

For a description of the completion rules, the completion header format, and completion status field values, refer to Section 2.2.9 of the PCI Express Base Specification.

Table 23.  Completion Signals for the Avalon-ST Interface

Signal

Direction

Description

cpl_err[6:0]

Input

Completion error from a PF or VF This signal reports completion errors to the Configuration Space. The SR-IOV Bridge responds to the assertion of these bits by logging the status in the error reporting registers of the Function and sending error messages when required. When an error occurs, the appropriate signal is asserted for one cycle. The individual bits indicate following error or status conditions:

  • cpl_err[0]: Completion timeout error with recovery. This signal should be asserted when a master-like interface has performed a non-posted request that never receives a corresponding completion transaction after the 50 ms timeout period when the error is correctable. The Hard IP automatically generates an advisory error message that is sent to the Root Complex.
  • cpl_err[1]: Completion timeout error without recovery. This signal should be asserted when a master-like interface has performed a non-posted request that never receives a corresponding completion transaction after the 50 ms time-out period when the error is not correctable. The Hard IP automatically generates a non-advisory error message that is sent to the Root Complex.
  • cpl_err[2]: Completer abort error. The Application Layer asserts this signal to respond to a non-posted request with a Completer Abort (CA) completion. The Application Layer generates and sends a completion packet with Completer Abort (CA) status to the requestor and then asserts this error signal to the Hard IP. The Hard IP automatically sets the error status bits in the Configuration Space register and sends error messages in accordance with the PCI Express Base Specification. The Application Layer generates and sends a completion packet with Completer Abort (CA) status to the requestor and then asserts this error signal to the Hard IP. The Hard IP automatically sets the error status bits in the Configuration Space register and sends error messages in accordance with the PCI Express Base Specification.
  • cpl_err[3]: Unexpected completion error. This signal must be asserted when an Application Layer master block detects an unexpected Completion. Many cases of unexpected completions are detected and reported internally by the Transaction Layer. For a list of these cases, refer to Transaction Layer Errors/
  • cpl_err[4]: Unsupported Request (UR) error for posted TLP. The Application Layer asserts this signal to treat a posted request as an Unsupported Request.The Hard IP automatically sets the error status bits in the Configuration Space register and sends error messages in accordance with the PCI Express Base Specification. Many cases of Unsupported Requests are detected and reported internally by the Transaction Layer. For a list of these cases, refer to Transaction Layer Errors.
  • cpl_err[5]: Unsupported Request error for non-posted TLP. The Application Layer asserts this signal to respond to a non-posted request with an Request (UR) completion. In this case, the Application Layer sends a completion packet with the Unsupported Request status back to the requestor, and asserts this error signal. The Hard IP automatically sets the error status bits in the Configuration Space Register and sends error messages in accordance with the PCI Express Base Specification. Many cases of Unsupported Requests are detected and reported internally by the Transaction Layer. For a list of these cases, refer to Transaction Layer Errors.
  • cpl_err[6]: Log header. If header logging is required, this bit must be set in the every cycle in which any of cpl_err[2], cpl_err[3], cpl_err[4], or cpl_err[5]is set. The header must be supplied on the inputs log_hdr[127:0].
cpl_err_fn[7:0] Input Specifies the function reporting the error on cpl_err[6:0].
cpl_pending_pf[<n>-1:0] Input

Completion pending from the PF. The Application Layer must assert this signal when a PF has issued one of more Non-Posted transactions waiting for completions. For example, when a Non-Posted Request is pending from PF0. cpl_pending_pf[0] records pending completions for PF0. cpl_pending_pf[1] records pending completions for PF1.

cpl_pending_vf[<n>-1:0] Input Completion pending from VF. The Application Layer must keep bit <n> asserted when the master block associated with Virtual Function <n> is waiting for Completion. For example, when a Non-Posted transaction is pending from VF <n>. <n> is the number of VFs.
log_hdr[127:0] Input When any of the bits 2, 3, 4, 5 of cpl_err is asserted, the Application Layer may provide the header of the TLP that caused the error condition. The order of bytes is the same as the order of the header bytes for the Avalon-ST streaming interfaces.
ko_clp_spc_data[11:0] Output The Application Layer can use this signal to build circuitry to prevent RX buffer overflow for completion data. Endpoints must advertise infinite space for completion data; however, RX buffer space is finite. ko_clp_spc_data is a static signal that reflects the total number of 16 byte completion data units that can be stored in the completion RX buffer.
ko_cpl_spc_header[7:0] Output The Application Layer can use this signal to build circuitry to prevent RX buffer overflow for completion headers. Endpoints must advertise infinite space for completion headers; however, RX buffer space is finite. ko_cpl_spc_header is a static signal that indicates the total number of completion headers that can be stored in the RX buffer.

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