Stratix V Avalon-ST Interface with SR-IOV PCIe Solutions: User Guide

ID 683488
Date 5/02/2016
Public

Visible to Intel only — GUID: ewo1430732421052

Ixiasoft

Document Table of Contents

11.1.3. Viewing the Important PIPE Interface Signals

You can view the most important PIPE interface signals, txdata, txdatak, rxdata, and rxdatak at the following level of the design hierarchy: altpcie_<device>_hip_pipen1b|twentynm_hssi_<gen>_<lanes>_pcie_hip.