Stratix V Avalon-ST Interface with SR-IOV PCIe Solutions: User Guide

ID 683488
Date 5/02/2016
Public
Document Table of Contents

1.1. Stratix® V Avalon-ST Interface with SR-IOV for PCIe Datasheet

Intel® Stratix® V FPGAs include a configurable, hardened protocol stack for PCI Express® that is compliant with PCI Express Base Specification 2.1 or 3.0. The Stratix V Hard IP for PCI Express with Single Root I/O Virtualization (SR-IOV) IP core consists of this hardened protocol stack and the SR-IOV soft logic. The SR-IOV soft logic uses Configuration Space Bypass mode to bypass the hardened Configuration Space. It implements the following functions in soft logic:

  • Configuration Spaces for up to two PCIe Physical Functions (PFs) and a maximum of 128 Virtual Functions (VFs) for both PFs
  • Base address register (BAR) checking logic
  • Support for the following interrupt types:
    • Message signaled interrupts (MSI) for PFs
    • MSI-X for PFs and VFs
    • Legacy interrupts for PFs
  • Support for Advanced Error Reporting (AER) for PFs
  • Support for Function Level Reset (FLR) for PFs and VFs
  • Support for x2, x4, and x8 links using a 256-bit Avalon-ST datapath
Figure 1.  Stratix V PCIe Variant with SR-IOV The following figure shows the high-level modules and connecting interfaces for this variant.
Table 1.  PCI Express Data Throughput

The following table shows the aggregate bandwidth of a PCI Express link for Gen1, Gen2, and Gen3 for supported link widths. The protocol specifies 2.5 giga-transfers per second for Gen1, 5.0 giga-transfers per second for Gen2, and 8.0 giga‑transfers per second for Gen3. This table provides bandwidths for a single transmit (TX) or receive (RX) channel. The numbers double for duplex operation. Gen1 and Gen2 use 8B/10B encoding which introduces a 20% overhead. In contrast, Gen3 uses 128b/130b encoding which reduces the data throughput lost to encoding to about 1.5%.

Link Width
×2 ×4 ×8

PCI Express Gen2 (5.0 Gbps) - 256-bit interface

N/A N/A

32

PCI Express Gen3 (8.0 Gbps) - 256-bit interface

N/A N/A

63

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