Stratix V Avalon-ST Interface with SR-IOV PCIe Solutions: User Guide

ID 683488
Date 5/02/2016
Public
Document Table of Contents

3.3. Base Address Register (BAR) Settings

Each function can implement up to six BARs. You can configure up to six 32-bit BARs or three 64-bit BARs for both PFs and VFs. The BAR settings are the same for all VFs associated with a PF.

Table 12.  BAR Registers

Parameter

Value

Description

Present (BAR0-BAR5) Enabled/Disabled Indicates whether or not this BAR is instantiated.
Type 32-bit address

64-bit address

Specifies 32- or 64-bit addressing.
Prefetchable Prefetchable

Non-prefetchable

Defining memory as Prefetchable allows data in the region to be fetched ahead anticipating that the requestor may require more data from the same region than was originally requested. If you specify that a memory is prefetchable, it must have the following 2 attributes:
  • Reads do not have side effects
  • Write merging is allowed

If you select 64-bit address, 2 contiguous BARs are combined to form a 64-bit BAR. You must set the higher numbered BAR to Disabled.

If the BAR TYPE of any even BAR is set to 64-bit memory, the next higher BAR supplies the upper address bits. The supported combinations for 64-bit BARs are {BAR1, BAR0}, {BAR3, BAR2}, {BAR4, BAR5}.

Size

16 Bytes–2 GB

Specifies the memory size.

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