Stratix V Avalon-ST Interface with SR-IOV PCIe Solutions: User Guide

ID 683488
Date 5/02/2016
Public
Document Table of Contents

5.10. Uncorrectable Error Severity Register

If a severity bit is 0, the core reports a Fatal error to the Root Port. If a severity bit is 1, the core reports a Non-Fatal error to the Root Port.

Table 64.  Uncorrectable Error Severity Register - 0x10C

Bits

Register Description

Default Value

Access

[31:21]

Reserved

0

RO

[20] Unsupported Request Received 0

RW

[19] ECRC Error Detected 0

RW

[18] Malformed TLP Received 1

RW

[17] Receiver Overflow 1

RW

[16]

Unexpected Completion was received

0

RW

[15]

Completer Abort (CA) was transmitted

0

RW

[14]

Completion Timeout

0

RW

[13]

Flow Control protocol error

1

RW

[12]

Poisoned TLP

0

RW

[11:5]

Reserved

0

RO

[4]

Data Link Protocol error

1

RW

[3:0]

Reserved

0

RO

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