Stratix V Avalon-ST Interface with SR-IOV PCIe Solutions: User Guide

ID 683488
Date 5/02/2016
Document Table of Contents

4.11. Local Management Interface (LMI) Signals

Use the LMI interface to write log error descriptor information in the TLP header log registers. The LMI access to other registers is intended for debugging, not normal operation.
Figure 19. Local Management Interface

The LMI interface is synchronous to pld_clk and runs at frequencies up to 250 MHz. The LMI address is the same as the Configuration Space address. The read and write data are always 32 bits. The LMI interface provides the same access to Configuration Space registers as Configuration TLP requests. Register bits have the same attributes, (read only, read/write, and so on) for accesses from the LMI interface and from Configuration TLP requests.

LMI writes may conflict with Host writes to the Configuration Space. When such a conflict occurs one of the accesses is successful and the other is dropped. The successful access cannot be determined a priori and no notification of success or failure is given to either the Application Layer or the Host.

All LMI reads are also held and executed when no configuration TLP requests are pending. The LMI interface supports two operations: local read and local write. The timing for these operations complies with the Avalon-MM protocol described in the Avalon Interface Specifications. LMI reads can be issued at any time to obtain the contents of any Configuration Space register. LMI write operations are not recommended for use during normal operation. The Configuration Space registers are written by requests received from the PCI Express link and there may be unintended consequences of conflicting updates from the link and the LMI interface. LMI Write operations are provided for AER header logging, and debugging purposes only.

Table 32.  LMI Interface






Data outputs. Valid when lmi_ack_apphas been asserted.



Read enable input.



Write enable input.



Acknowledgment for a read or write operation. The SR-IOV Bridge asserts this output for one cycle after it has completed the read or write operation. For read operations, the assertion of lmi_ack also indicates the presence of valid data on lmi_dout.



Byte address of 32-bit configuration register. Bits [1:0] are not used.

lmi_func[8:0] Input Bit [8] directs the LMI read or write operation to either the Hard IP or the Function configuration spaces implemented in the SR-IOV Bridge. The following encodings are defined:
  • 1b'0: LMI access to registers in Hard IP block
  • 1'b1: Access to configuration registers in the SR-IOV Bridge

Bits [7:0] specify the function number corresponding to the LMI access. Used only when the LMI access is to a configuration register in the SR-IOV Bridge.



Data inputs.

Figure 20. LMI Read
Figure 21. LMI Write The following figure illustrates the LMI write. Only writable configuration bits are overwritten by this operation. Read-only bits are not affected. LMI write operations are not recommended for use during normal operation with the exception of AER header logging.

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